Instrumentation Development Laboratory
SciFi Tracker
Hardware Design Reference
Author: Peter Orel
Checked by: Gary S. Varner
Approved by: Gary S. Varner
Tuesday, February 9, 2016
Table of Contents
1
Introduction .......................................................................................................................................... 3
2
The MPPC photo detector .................................................................................................................... 4
3
2.1
Modeling the MPPC ...................................................................................................................... 4
2.2
Hamamatsu S10362-11-100p MPPC ............................................................................................. 5
Design considerations for the Daughter Card....................................................................................... 6
3.1
4
5
The preamplifier............................................................................................................................ 6
3.1.1
Differential configuration...................................................................................................... 6
3.1.2
Singe ended configuration .................................................................................................. 11
3.1.3
Layout considerations ......................................................................................................... 11
3.1.4
Using the LMH6703 ............................................................................................................. 13
3.2
The TargetX interface .................................................................................................................. 15
3.3
DACs ............................................................................................................................................ 17
3.4
Power Supply .............................................................................................................................. 18
Design considerations for the Motherboard (IDL_14_36) .................................................................. 19
4.1
Board dimensions and layout ..................................................................................................... 19
4.2
On-board Diagnostics.................................................................................................................. 20
Design considerations for the Power board (IDL_14_42) ................................................................... 21
5.1
Intermediate switching PS .......................................................................................................... 21
5.2
Other rails ................................................................................................................................... 24
2
1 Introduction
This document will serve as a repository for all major considerations involving the hardware design.
The goal of this project is to develop a detector box which will track the position of the incident highenergy muons.
The hardware of the detector box can be segmented into three distinct sub-segments:
1. The Scintillator Bicron DC408 and the MPPC photodiode circuit
2. The Analog electronics for signal conditioning and acquisition
3. The digital back-end with the TARGETX digitizer and the SCROD processing board
The following figure shows the block scheme of the detectors box:
3
2 The MPPC photo detector
The MPPC sensor is based on a pixel array of avalanche photodiodes. These photodiodes can be biased
with a reverse voltage that is greater that the breakdown voltage of the photodiodes themselves. This is
called the Geiger mode of operation. In this mode the electric field at the p-n junction in the photodiode
is very strong. When even a single photon gets absorbed and creates an electron/hole pair, the electron
gets accelerated by the field and gains sufficient energy to collide with the crystal lattice which generates
another electron/hole pair. This pair gets accelerated again and through the same process creates other
pairs. This process (Impact ionization) can continue as long as the number of colliding pairs is greater than
those being collected in the p and n substrates [1].
The process is of a rather digital nature. It does not depend on the number of photons incident on a single
p-n junction. One photon can trigger the process which is then self-sustaining until the bias voltage falls
below the breakdown voltage.
There are a few issues around such a design:
1. Temperature dependence
With higher temperature the vibrations in the lattice become stronger which makes it difficult
for the ionization to occur so the temperature should be monitored and the reverse voltage
corrected accordingly.
2. Dark current
The Carriers can be generated by the thermal excitation which makes for false pulses. This again
is dependent on the ambient temperature.
2.1 Modeling the MPPC
The MPPC pixel is non-linear in nature but can be modeled with the circuit shown in the following figure:
This model can be analyzed in three different states of
operation.
1. PRE-DISCHARGE STATE
The SW switch is opened and the Cdiode is charged
2. DISCHRAGE STATE
The SW switch close when a photon-electron causes the
avalanche. The Cdiode discharges through Rdiode. The
pulse current rises until voltage at Cdiode/Rdiode terminal
reaches Vbr. After that the avalanche dies out and the SW
opens.
3. RECOVERY STATE
After the SW opens, the Cdiode slowly recharges until the
Cdiode/Rbias terminal voltage reaches Vb again. At this
point the MPPC is ready to be fired again [3][4].
Figure 1: MPPC equivalent circuit model
4
2.2 Hamamatsu S10362-11-100p MPPC
In our case we are working with a Hamamatsu MPPC chip with part number S10362-11-100p. This chip
has 100 pixels connected in parallel. This means that the pulse height depends on the number of pixels
discharging at the same time.
Every photodiode has a parameter called the gain which tells us how much charge is generated by one
photon-electron normalized in units of elementary charge q=1.602*10-19. This parameter is dependent on
temperature and can be stabilized by driving the reverse bias voltage accordingly.
In case of the S10362-11-100p:
G=2.4*106 @70Vr which means that 𝑄 = 𝐺 ∙ 𝑞 = 3.845 ∙ 10−13 𝐶 per photon-electron.
On the other hand 𝑄 = 𝐶 ∙ (𝑉𝑅 − 𝑉𝐵𝑅 ), where C = 35 pF which means that 𝑉𝑅 =

𝑄−𝐶𝑉𝐵𝑅
𝐶
= 70.0096 𝑉
A gain/temperature dependence curve measurement could be part of the calibration procedure
for every MPPC module. This would require driving the box in a temperature chamber or redesign
the MPPC module to include temperature stabilization and driving. One elegant solution for this
is by using thermoelectric cooling and a simple PI regulator and TEC driver.
By looking at the datasheet information we can assume that the pulse ramp-up time is on the order of a
nanosecond. By integrating the charge built-up in time 𝐼𝑝𝑢𝑙𝑠𝑒 = 𝑡
𝑄
𝑟𝑎𝑚𝑝
= 0.385 𝑚𝐴. This is the current
pulse amplitude for a single pixel. In the worst case, where all pixels are active together the pulse
amplitude would get higher by 100 times. Therefore the dynamic range that needs to be covered is form
Ipmin = 0.385 mA to Ipmax = 38.5mA.
Another implication to be considered is the bandwidth which is defined by the rise time to bandwidth
approximation 𝑡𝑟 ≅
0.34
.
𝐵𝑊
In our case the rise time is on the order of a nanosecond we can approximate
the bandwidth to be on the order of 340 MHz. However due to the energy spread in time of the pulse the
rise time and consequently the bandwidth requirements can be loosened to about a bandwidth of
approximately 100MHz.
The design consideration are based on a specific MPPC part. All of the equations have been taken form
the Hamamatsu technical note [2].
5
3 Design considerations for the Daughter Card
3.1 The preamplifier
The preamplifier is meant to condition the signal coming from the MPPC array as well as provide the
necessary biasing conditions for the MPPC to work in the first place. This can be realized in two different
ways: By having a differential configuration where both the bias and termination resistors are equal
(balanced input) and by having a single ended configuration where the termination resistor is much
lower than the bias resistor and the transmission line is single ended, where the biasing line is for
biasing purposes only.
3.1.1 Differential configuration
In the differential configuration the sampling circuit is connected to the terminal ends of the MPPC. The
figure 2 shows an example of this circuit:
Figure 2: Differential configurator of the pre-amplifier circuit
The voltage pulse amplitude is defined by the both the Rbias and Rterm values which need to be equal in
order to have a symmetric pulse response so that the differential configuration works properly since, in
𝑅
our case, its output follows the equation 𝑉𝑂𝑈𝑇 = 𝑅𝐹 (𝑉+ − 𝑉− ). The pulses are opposite in polarity to each
𝐺
other, figure 3.
6
Figure 3: Voltage pulses as seen from preamplifier input (AC coupling), Brown is the Anode and Green is the Cathode
This configuration has some advantages and some drawbacks:
Advantages:


The signal can be routed differentially which is good for common-mode disturbance rejection
Lower gain (factor of 2) required on the pre-amp which is better in terms of GBW product
requirement
Drawbacks:

3.1.1.1
The Rterm and Rbias need to be equal which removes the flexibility of setting the proper resistors
for the pinching current of the MPPC and at the same time having the desired signal range.
Simulating the differential configuration.
For simple estimation purposes, the simplest model, which covers the discharge state only, is that of a
current source generator in series with the bias and termination resistors. In the discharge mode the
photodiode operates in the reverse bias mode, therefore the current source direction is also in the reverse
direction.
7
Figure 4: MPPC model and pulse waveform
The simulation has been done in TINA (Texas Instruments SPICE simulator).
Four operational amplifiers have been evaluated:




Texas Instruments, THS4304
Texas Instruments, THS3202
Texas Instruments, LMH6703
Texas Instruments, OPA694
The THS4304 is a voltage feedback amplifier with very high bandwidth but slow slew rate. It is less
demanding in terms of feedback components which makes it more stable and more reliable.
The THS3202, LMH6703 and OPA694 have current feedback architectures which allows for a higher slew
rate which makes it perfect for pulsed signals. However their stability is dependent on feedback
component selection. The following table summarizes some key parameters of all four op-amps:
8
Parameter
Bandwidth
Slew rate
V. Noise
Quiescent current
Input Offset v.
THS4304
3 GHz @G=1
830 V/µs @1V
2.4 nV/√Hz
18 mA
±4 mV
THS3202
1.8 GHz @G=1
5100 V/µs
1.65 nV/√Hz
16.8 mA
±3 mV
LMH6703
1.8 GHz @G=1
4200 V/µs
2.3 nV/√Hz
11 mA
±1.5 mV
OPA694
1.5 GHz @G=1
1700 V/√Hz
2.1 nV/√Hz
6 mA
±3 mV
The simulation was done with a pulse rise time of 1ns and a fall time of 20ns.
The following figures show the transient and frequency responses:
Figure 5: Output Transient response for the four op-amps
9
Figure 6: Output Frequency response for the four op-amps
The bandwidth spans are summarized in the following table:
Part
THS4304
THS3202
LMH6703
OPA694
Low cutoff [kHz]
32.15
32.10
31.78
31.78
High cutoff [MHz]
259.60
214.00
281.00
148.71
The noise of this configuration is estimated using the formulas given in a Texas instruments application
note [5].
The input referred noise for each op-amp and its configuration is given in the following table:
Part
THS4304
THS3202
LMH6703
OPA694
IRN [nV/√Hz]
3.82
6.87
6.75
10.32
Integrated [mV]
0.064
0.100
0.113
0.173
𝐴
The signal-to-noise ratio could be estimated at 𝑆𝑁𝑅𝑂𝑈𝑇 = 20 ∙ log10 ( 𝐴𝑠𝑖𝑔𝑛𝑎𝑙 )
𝑛𝑜𝑖𝑠𝑒
.However considering
that the noise flour of the pulse signal is at approximately 2mV. Considering unity gain for the signal noise,
the total sum of the noise signal and the pre-amp noise is 2.0121 mV so the SNR would be 19.63 dB.
10
3.1.2 Singe ended configuration
The single ended configuration would be done such that the Rbias and Rterm would be different. The
Rbias would be a high value resistor in the region of kΩ, while the Rterm would be a 50Ω resistor. A
coplanar transmission wave guide would lead the signal from the MPPC to the pre-amplifier input.
Alternatively a balun can be used to transform the signal into a differential signal. The figures 9 and 10
show this configurations.
If VBR=70V, for a 50Ω Rbias the voltage bias should be 𝑉𝑏𝑖𝑎𝑠 < (𝑉𝐵𝑅 + 𝑅𝑏𝑖𝑎𝑠 ∙ 𝐼𝑀𝐼𝑁 ) which for this specific
application is 70.0193V. This can be achieved with a DAC that has a LSB lower that half the voltage step
which is approximately 10mV. At 5V dynamic range this means a 9-bit DAC or better. However if we look
at the MPPC datasheet we can see that the breakdown threshold voltage has temperature dependence
of 56 mV/°C which means that we don’t have any margin on the Vbias set-point. This can be solved by
driving the Vbias through a regulation loop which follows the temperature change close to the MPPC
array. However this can also be problematic since it would essentially be a positive feedback loop, where
we increase the Vbias as Vbr increases and Vbr will increase with temperature which also likely to increase
if no temperature control is implemented. Also Vbias would eventually saturate.
NOTE: Each MPPC has a specified VBR which is given on the factory test sheet accompanying the MPPC.
The example given is just for illustrative purposes.
3.1.3 Layout considerations
The layout has been done such that by choosing the assembly variant we can switch from one
configuration to the other as seen in the following figures.
Figure 7: Single-ended configuration
11
Figure 8: Differential configuration
The transmission line has been modeled using Mentor graphics Hyperlinks. When used in the differential
configuration the transmission line is differential and has differential impedance of approximately 100Ω
On the other hand when used in a single-ended configuration where one of the lines is used for biasing
only the single-ended impedance of the termination line is approximately 60Ω.
The ground planes have been cut from underneath the feedback loop and input pins of the amplifier to
minimize the parasitic capacitances to ground.
Figure 9: Pre-amplifier layout considerations
12
3.1.4 Using the LMH6703
The LMH6703 is a current feedback amplifier. The stability of the feedback loop is dependent on the value
of RF. For this particular package a reasonable value has been obtained by looking at the datasheet figure
29 [6], which is also presented here:
Figure 10: Recommended RF vs Gain
This way a resistor of 590Ω has been chosen. It is to be noted that if the Gain is to be changed, this figure
has to be taken into account when choosing the new values for RF and RG.
The stability of a current feedback op-amp is dependent on the feedback resistor. Its internal structure is
shown in the following figure:
Figure 11: Current feed-back simplified structure
The transfer function for this model is given as [8]:
13
𝛼(𝑠) (1 +
𝐻𝐶𝐹 =
1+
𝑅𝑓
)
𝑅𝑔
𝑅𝑓
𝑅𝑓 + 𝑅𝑖 ∙ (1 + 𝑅 )
𝑔
𝑍(𝑠)
As we can see the forward transimpedance has to be high enough that the gain at low frequencies is
simply the feedback loop gain 1+Rf/Rg. At high frequencies the Z(s) starts to show by rolling off the gain
slope.
For our particular configuration (differential) we essentially need to solve the same equations:
𝐻𝐷𝐼𝐹𝐹
𝑍𝐹+
𝑍𝐹+
𝑍𝐺+ + 𝑍𝐹+ 𝑍𝐺+ + 𝑍𝐹+
+
1
𝑍𝐹−
𝑍𝐺−
=
∙
1
1
𝑍
𝑍
+
(1 + 𝑖 + 𝑖 ) 𝑠𝐶𝑂𝑈𝑇
𝑍𝐹− 𝑍(𝑠) + 𝑅𝐼𝑆𝑂
𝑍𝐹− 𝑍𝐺−
Where
𝑍𝐹+ =
𝑅𝐹+
1 + 𝑠𝑅𝐹+ 𝐶𝐹+
𝑍𝐹− =
𝑅𝐹−
1 + 𝑠𝑅𝐹− 𝐶𝐹−
𝑍𝐺+ = 𝑅𝐺+
𝑍𝐺− = 𝑅𝐺−
1
And the input buffer impedance is 𝑍𝑖 = 𝑅𝑖 + 𝑠𝐶 , where Ri is given to be 30Ω and Ci is 0.8pF.
𝑖
The forward transimpedance Z(s) has been extrapolated form the spice model and its transfer function
is given as:
𝑍(𝑠) =
4.615𝑒29𝑠 9 + 6.894𝑒40𝑠 8 + 3.836𝑒51𝑠 7 + 9.73𝑒61𝑠 6 + 1.13𝑒72𝑠 5 + 6.293𝑒81𝑠 4 + 1.961𝑒91𝑠 3 + 5.054𝑒100𝑠 2 + 6.522𝑒109𝑠 + 8.253𝑒118
2.4e − 12s13 + 0.391s12 + 2.46e10s11 + 7.563e20s10 + 1.216e31s9 + 1.092e41s8 + 5.837e50s7 + 2.045e60s6 + 5.261e69s5 + 9.369e78s4 + 1.142e88s3 + 8.479e96s2 + 4.627e103s
With a frequency response shown in the following figure:
Bode Diagram
Magnitude (dB)
300
200
100
0
Phase (deg)
-100
-90
-180
-270
-360
2
10
4
10
6
10
8
10
10
10
Frequency (Hz)
Figure 12: LMH6703 forward transimpednace frequency response
14
3.2 The TargetX interface
The output of the Preamplifier is fed into a dedicated time domain waveform digitizer IC called the
TargetX. The TargeX has 16 channel inputs that are referenced to a pedestal voltage called VPED which can
span from 0.4V to any value up to 2.4V. This also determines the input voltage dynamic range since the
upper limit is Vcc at 2.5V. In our case VPED has been connected to a LDO sourcing 0.817V. There is also an
option of driving this voltage with a DAC.
Input protection has been achieved with schottky diodes with approximately 1ns response time.
The input line geometry has been chosen to accommodate the chosen board stack-up. The transmission
line has an impedance of approximately 65Ω.
The analog input of the TargetX can be modeled in similar way to the input of the Labrador AISC [7], as is
shown in the following figure:
Figure 13: Approximation of the equivalent input circuit for the TargetX
This circuit has been simulated in ADS. The S11 of the input can be shown in the following figure:
15
Figure 14: TargetX S11 with 28Ω
As we can see at the frequency of interest the input impedance is approximately 33Ω with an inductive
affinity. If we remove the resistor:
Figure 15: TargetX S11 with 1MΩ
The input impedance becomes almost entire inductive. However if we simply terminate then line at the
input with a 64.9Ω resistor:
16
Figure 16: TargetX S11 with input termination
We can see that S11 is very nicely matched resulting in very low reflection. It has to be noted that at higher
frequency it presents a capacitive affinity. So for working at higher frequencies this too would have to be
compensated.
The digital interface of the TargetX is directly interfaced to the FPGA featuring a 2.5V logic with two
dedicated LVDS25 clocks. The LVDS lines are routed differentially and terminated at the TargetX inputs.
3.3 DACs
The DACs in this case are used to fine tune the VBR voltage on the MPPC. As has been shown a minimum
of a 9bit DAC is necessary to achieve the necessary resolution. We chose the Texas Instruments
DAC128S085 which is a 12bit SeriaSPI 8-Channel DAC. It can swing from 0 to 5V and source/sink a
continuous current of 10mA per Channel. Its output noise spectral density is 40 nV/√Hz which integrated
in our bandwidth of interest is approximately: 0.67mV.
For SW requirements please see document: CSciFi DACdriving.docx
17
3.4 Power Supply
For Heat dissipation reasons it has been decided that all of the voltage rails will be generated outside the
board. The following table summarizes the voltage rails and their worst case current load:
Voltage [V]
+2.5
+4.5
-4.5
Current [mA]
280
169
169
Power [W]
0.7
0.76
0.76
Σ=2.22
Every daughter card has a worst case power consumption of 2.22W.
18
4 Design considerations for the Motherboard (IDL_14_36)
The motherboard has more mechanical considerations than electrical. The motherboard is meant to be
an interconnection plane between SCROD, the daughter-cards and the power supply board.
4.1 Board dimensions and layout
The board dimensions are constrained by the scintillator dimensions in one corner and SCROD dimension
and runway in the other corner. In comparison with the previous board this version has been reduced by
approximately 40% in area.
The board has 8 layers and is 2mm thick in order to reduce the possibility of curving during daughter-card
insertion. The layer stack has been chosen so that it has 4 signal layers with reference planes on top and
bottom to have good impedance control of the signal lines on the analog side. The reference planes are
divided into two pairs of ground and power planes respectively.
The geometry of the lines has been calculated such that the impedance matches the impedance of the
lines on the daughter-cads consequently reducing the risk of mismatches and signal distortion.
The layout is done such that the analog signals form the MPPC array and the digital signals form the
daughter cards never intersect. The grounding is sliced so that the actual intersection is close to the
intersection on the daughter-boards as it can be seen in the following figure:
Figure 17: Ground plane of the motherboard
19
The analog signal routing between the daughter-cards and the MPPC array has been scrambled so that
crosstalk between adjacent channels is minimized.
The estimated highest difference in propagation delay within one group is approximately 0.5ns.
The clocks are routed differentially. The maximum difference in propagation delay between the clocks is
approximately 163ps.
4.2 On-board Diagnostics
The on-board diagnostic includes:



Three temperature sensors
o Two are located close to the MPPC boards
o One is locate on the bottom side just above the FPGA of the SCROD board.
4 channel ADC for monitoring the power supply rails (2V5, +5VA, +5VSC, -5VA, HV_BIAS)
Auxiliary general purpose TTL compatible clock input/output buffer that is connected to global
clock input/output on the SCROD FPGA.
The ADC and temperature sensors are connected to the FPGA via a dedicated I2C interface.
20
5 Design considerations for the Power board (IDL_14_42)
The power supply board has been designed to provide all of the power rails necessary for the
Motherboard, SCROD and daughter card and MPPC to work properly. A block scheme is shown below:
Figure 18: Power board block scheme
All rails are generated form the input 5V rail. To increase the efficiency a configuration of switching and
linear power supplies has been used. Most of the ICs are form Linear Technology.
5.1 Intermediate switching PS
In order to improve efficiency for the conversion to +2.5V and -5V respectively an intermediate switching
power supply topology has been used.
In order to reduce costs a single IC has been chosen that covers both configuration (SEPIC and Inverting).
The IC is form Linear technology LT3956 which has an integrated MOSFET capable of switching up to 5A
of current [9]. The IC has multiple configuration options.
We chose the SEPIC (Single-ended primary-inductor converter) option for to transform the +5V rail to an
intermediate voltage of +3V. The SEPIC converter is a type of DC-DC converter allowing the electrical
potential (voltage) at its output to be greater than, less than, or equal to that at its input; the output of
the SEPIC is controlled by the duty cycle of the control transistor. A SEPIC is essentially a boost converter
followed by a buck-boost converter, therefore it is similar to a traditional buck-boost converter, but has
advantages of having non-inverted output (the output has the same voltage polarity as the input), using
a series capacitor to couple energy from the input to the output (and thus can respond more gracefully to
a short-circuit output), and being capable of true shutdown: when the switch is turned off, its output
drops to 0 V, following a fairly hefty transient dump of charge. The IC has been configured to switch at a
frequency of approximately 0.6MHz. Its output efficiency is in the range of 95%.
21
Figure 19: Simplified SEPIC feedback loop
The output is then followed by a LDO (LT1764) which is a 3A linear low drop regulator. The LDO converts
the 3V of the switcher to the 2.5V rail. Its conversion efficiency is approximately 86%. Higher efficiency is
limited by the voltage drop-out voltage.
At the SEPIC side careful consideration is to be given to the selection of the inductor and diode:


The inductor has to be able to handle the current therefore its saturation current has to be higher
than the maximum current of the application. It is usually good to have at least 10% of reserve
(more is better). The value of the inductance is more flexible but has to be such that at the
operating frequency the calculated magnitude of the current wave does not fall off the limits
imposed by the maximum and minimum current operation…usually is good to have at midrange
if not otherwise specified. If more than one inductor is to be used (like in our case), it is very good
in terms of loop compensation that the inductors are coupled in a dual-winding configuration.
The diode plays an important role in the overall efficiency of the converter. The diode has to be
fast enough and at the same time be able to handle the current we need. Usually schottky type
diodes are the most adequate with switching speeds in the ns range and current handling in
amperes. It is also very important to have low forward voltage since the voltage drop over the
diode multiplied by the current is the power dissipated by the diode.
Our application has been simulated in LTspice. The results are shown in the figure below:
Figure 20: LTspice SEPIC simulation
22
The green line is the output of the SEPIC regulator. As we can see it has programed slow start of 48ms and
it stabilizes to something lower to 3V. The output ripple is approximately 12mV. The blue line shows the
output of the LDO following the switcher stage. Together with the low-ESR output capacitance of the
switching station the ripple is reduced to approximately 5μV.
Another special consideration is the layout of the switching stage
Figure 21: SEPIC layout
The layout has to be done such that the switching currents (both forward and return) of the two loops
remain confined around the controller and the inductors. Also to insure a good conductive return path a
solid ground plane under all of the controller layout is recommended. Low-ESR decoupling is ensured on
both the input and output. This done by placing ceramic (low-ESR) and tantalum (bulk-capacitance) close
to the inputs and output of the controller loops.
For the negative supply the consideration are similar however the loops are a little bit different. The
output loop is done such that the positive side of the current waveform is clipped and only the negative
reaches the output inductor which then performs the task of integration into the output voltage.
The negative switching stage is similarly followed by a LDO designed to filter the ripple of the switching
stage. The output ripple is on the order of 8mV. It is lower that the SEPIC stage duo to its topology of
having the output voltage exiting on the output inductor. The filtered LDO output is on the same order of
magnitude as the SEPIC one. The conversion efficiency of the LDO is around 85%.
23
5.2 Other rails
The positive analog +5V voltage is generated with an LDO directly from the main input. The LDO used is
the same as for the second stage of the SEPIC converter. Its conversion efficiency is on the order of 90%.
The integrated noise of these LDOs is on the order of 40μV.
The SCROD is powered directly from the input which is filtered through an LC filter.
The High voltage power supply is the EMCO SIP90. This too is powered directly from the input which is
filter through a similar LC filter. It operates from a minimum of 25V up to something over 90V. It has a
declared voltage ripple of 5mV and can source of up to 1mA of current. Its output voltage can be driven
and has slope that is defined by the following equation:
𝑉𝐻𝑉 = 90.5 − 14.1 ∙ 𝑉𝐷𝐴𝐶
This means that the slope is negative:
100
5000mV REF
4096mV REF
90
High Voltage Out [V]
80
70
60
50
40
30
20
0
0.5
1
1.5
2
2.5
3
DAC voltage [V]
3.5
4
4.5
5
Figure 22: Programing voltage vs the output voltage
As seen from the figure above the slope is negative. The DAC chosen to drive SIP90 is the DAC128S085
from Texas Instruments. It is a 12bit single channel DAC. It has been chosen because it wakes up at middle
of the internal reference which is 4.096V. Alternatively it can be SW configured to use the supply rail of
5V as reference. For more info on the DAC please see document: CSciFi DACdriving.docx.
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All of the rails are power off at startup except the SCROD supply. The enable function is implemented in
the SCROD.
The input protection consists of a fuse in series and a diode in parallel. The fuse is a PTC with trip current
around 8A. The diode is the same schottky diode used for the switching converters. It can handle a
continuous short circuit current of 5A.
The board is a 2 layer board with all of the components on one side in order to reduce cost. Most of the
connections are routed on the top layer. The bottom layer serves as a ground plane. The copper thickens
has been chosen to be 55μm due to the high current specifications.
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References
[1]. Brian F. Aull, et. All, “Geiger-Mode Avalanche Photodiodes for Three-Dimensional Imaging”, MIT
2002.
[2]. Hamamatsu Technical Information Sheet, “MPPC, MPPC modules, (http://www.hamamatsu.com/)
[3] Fabrice Retière, “MPPC Response Simulation and High Speed Readout Optimization”
[4] Stefan Seifert, et. All, “Simulation of Silicon Photomultiplier Signals”
[5] James Karki, TI, “Calculating noise figure in op amps”
[6] http://www.ti.com.cn/cn/lit/ds/symlink/lmh6703.pdf
[7] G.S. Varner, et. All, “The Large Analog Bandwidth Recorder and Digitizer with Ordered Readout
(LABRADOR) ASIC”
[8] Texas Instruments, “OA-13 Current Feedback Loop Gain Analysis and Performance Enhancement”
[9] Linear Technology, “http://www.linear.com/product/LT3956”
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