EECS 373 Midterm
Winter 2011
Name: ____________________________________
unique name: _______________
Sign the honor code:
I have neither given nor received aid on this exam nor observed anyone else doing so.
___________________________________
Scores:
# Page
2
3
4
5
6
7
8
9
Total
Points
/12
/10
/18
/10
/15
/12
/12
/12
/100
NOTES:
1.
2.
3.
4.
5.
6.
Closed book/notes.
There are 9 pages including this one.
Calculators are allowed, but no PDAs, Portables, Cell phones, etc.
Don’t spend too much time on any one problem.
You have about 80 minutes for the exam.
Be sure to show work and explain what you’ve done when asked to do so.
 Getting partial credit without showing work will be rare.
7. Throughout the exam “standard logic gates” means arbitrary input ANDs, ORs,
NANDs, NORs, XORs and XNORs as well as NOT gates.
1
1. Fill-in-the-blank or circle the best answer. [12 points, -2 per wrong or blank answer]
a) A 25 MHz clock with a duty cycle of 25% is high for ___0.01____________ µs per cycle.
(Notice the unit!)
b) Differential signaling over a twisted pair of wires is used in a number of modern buses to
REDUCE THE IMPACT OF EXTERNAL NOISE / make it easier to not have a shared clock /
implement wired-OR encoding / increase the speed of the data lines.
c) Manchester encoding is used to GET BOTH DATA AND CLOCK ON A SINGLE WIRE / reduce the
impact of external noise / act a termination scheme to reduce the impact of weak signals.
d) One of the assembly directives we have used is “.syntax unified”. This tells the
assembler that we are using one or more a high-level languages and assembly / we are
using all registers rather than just r0-r7 and r13-r16 / WE USING AN ASSEMBLY LANGUAGE THAT
SUPPORTS MORE THAN ONE ISA / this file includes the main.
e) The assembler converts __.S______ files into __.O_____.
(For this question each answer should be one of: “.s”, “.c”, “.ld”, “.bin”, or “.o”)
f)
On the AHB, the NONSEQ transaction type is used FOR A SINGLE TRANSFER OR THE FIRST
TRANSFER OF A BURST / when no transfer is requested / for each transfer after the first in a
burst / when HSIZE=2’b10.
g) 0xfffc is -3 / -4 / -5 / 16523 / 12 as a 16-bit two’s complement number.
2
2. Circle all the registers which are callee-save on the ARM. Please only circle the entries in the first
column and only worry about registers r0-r12. [3 points]
3. Write ARM assembly code which performs the same task as the following code segment. Your code
must be no longer than 10 assembly instructions. [6 points]
#define REG_FOO 0x40000140
uint32_t *reg = (uint32_t *)(REG_FOO);
*reg += 3;
mov
movt
ldr
add
str
r3,
r3,
r4,
r4,
r4,
#0x0140
#0x4000
[r3]
#3
[r3]
3
4. Write an ARM assembly language procedure that implements the following C function in an EABIcompliant manner and conforms to the following signature. Clearly comment your code so we can
figure out what we are doing and what value each register holds. Poorly commented/unclear code
will get points removed. [18 points]
uint32 ICD55(uint32 a[], uint32 b, uint32 j)
{
if(a[j]>55)
j=check(a[j],b)+j;
return(j+b);
}
if
doneif:
push {r5, r6, r7, lr}
mov r5, r2
mov r6, r1
mult r5, #4
ldr r0, [r0,r5]
cmp r0, #55
bhi if
mv r0, r5
b done_if
bl check
add r0, r5
add r0, r6
pop{r5, r6, r7, pc}
// also r7 just to keep stack aligned
// r5 is now j
// r6 is now b.
//
//
//
//
r0 is now a[j]
\ Compare unsigned, branch if
/ a[j]>55.
set r0=j
// r0= check(a[j],b)+j
// r0= j+b
// restore and return.
4
5. Design a device which takes an input clock of 20MHz and outputs a 1MHz clock with a 40% duty
cycle. You may use n-bit binary counters, D flip-flops with synchronous reset. You may express
combinational logic as a Boolean expression or use standard logic gates. Label and write clearly.
[10 points]
D Flip-Flop
5-bit counter
<8
Q[4:0]
Q Clock out
Clock
=19
Clock in
Clock
R
<8
=19
(!Q3*!Q4)
Q4*!Q3*!Q2*Q1*Q0
5
6. Consider the ARM assembly found below. Assume that r3=0xAABBCCDD, r1=0x00001000, and all
other registers and memory locations are initialized to zero.
str r3, [r1,1]
ldrb r5, [r1],#2
orr r5, r5, #0xF
strh r3, [r1,#-4]!
ldr r3, [r1]
What are the values of these registers? You must write your answers as 8-digit hex numbers if
you wish to receive credit! [9 points, 3 each, no partial credit]
i. r1=___0x00000FFEE_____
ii. r3= ___0xDD00CCDD____
iii. r5=___0x0000000F_______
7. Consider a device which has been placed on an arbitrary 8-bit address bus (called ADS[7:0]) and is to
respond to any address in the range 0x20 to 0x27. Using only standard gates, design a device that
will generate a “1” when this device has been addressed. Your device should be as simple as
possible and may ignore any signals on the bus other than ADS. Be sure to clearly label your inputs
(as ADS7 through ADS0) and your output (as “OUT”). [6 points]
ADS7
ADS6
ADS5
ADS4
ADS3
OUT
6
8. Write a C function int is_pending(int x) that returns a 1 if interrupt source x is pending.
You need not check to be sure the value x is reasonable. The table below may prove useful.
[12 points]
int is_pending(int x)
{
unsigned int ISPR_add = 0xE000E200; // or 0xE000E280
unsigned int index=x>>5;
unsigned int offset=x & 0x1F;
unsigned int *address= (unsigned int *) (ISPR_add+4*index);
return( (*address>>offset)&0x1);
}
7
9. Consider the following Thumb2 entries taken from the ARMv7-M Architecture Reference Manual.
[12 points]
a) Using the above, write the hex encoding for ADD r9, r9, r11. [4]
0x44D9
b) Using the above, decode 0x50F0 into an assembly instruction. [3]
STR r0, [r6,r3]
c) There exists a 32-bit version of the STR instruction with the same assembly format
(STR <Rt>,[<Rn>, <Rm>]). When would the 32-bit version be used rather than the
above 16-bit version? Why do both a 16-bit and 32-bit version exist? [5]
THIS ENCODING ONLY ALLOWS US TO TALK TO REGISTERS R0-R7. IF WE WANT TO TALK TO OTHERS,
WE NEED A DIFFERENT ENCODING .
8
10. You are working on a design for our SmartFusion which has 5 interrupt sources: A, B, C, D, and E.
Recall that the SmartFusion only implements the 5 highest priority bits, the other 3 are ignored. You
want the following to be true: [12 points]
 A should be able to preempt all the other interrupts
 B should have the highest priority other than A in the event of a multiple pending interrupts.
 C should have the highest priority other than A & B in the event of a multiple pending interrupts.
 D should have the lowest priority other than E in the event of a multiple pending interrupts.
 E should have the lowest priority and all the other interrupts should be able to preempt it.
a) List all PRIGROUP setting or settings you could use in this case. Assume no two interrupts
can be assigned the same priority. Provide your answer in 3-digit binary and explain. [6]
b) Indicate, in 8-bit binary, what priorities you will assign to each interrupt. Let us know which
PRIGROUP setting you are using (mainly if you have more than one PRIGROUP listed above).
Again, no two interrupts may be assigned the same priority. [6]

PRIGROUP=________________________ (3-digit binary)

A priority= ________________________ (8-digit binary)

B priority= ________________________ (8-digit binary)

C priority= ________________________ (8-digit binary)

D priority= ________________________ (8-digit binary)

E priority= ________________________ (8-digit binary)
9