Design and Simulation of FPGA Based BPSK and BASK
Modulators Using VHDL
Swam Yee
Department of Electronic Engineering
Mandalay Technological University
Abstract - This paper describes binary phase-shift keying
(BPSK) and binary amplitude-shift keying (BASK)
modulation schemes by using Very High Speed Integrated
Circuit (VHSIC) Hardware Description Language (HDL),
known as VHDL, in Quartus 7.2 software. Modulation is the
process used for data transmission,and by means of this, the
message data is conveyed by the sinusoidal carrier signal. By
using VHDL, Field Programmable Gate Arrays (FPGAs)
can be used in many different purposes. FPGAs are very
efficient devices for different kinds of areas in electronic
field. In this paper, the BPSK modulator and BASK
modulator designed by using VHDL and it is purposed for
FPGA devices.
Keywords - BPSK, BASK, FPGA, Modulation, VHDL
I. INTRODUCTION
VHDL is a language used for digital electronic systems,
arising out of the United States Government’s Very High Speed
Integrated Circuits (VHSIC) program, which is initiated in
1980. Then, the developing of VHDL was very fast and became
a standard of the Institute of Electrical and Electronic Engineers
(IEEE) in the US. The advantages of using VHDL are allowing
the description of the design structure, allowing the
specifications of the functions of designs using familiar
programming languages forms, and allowing the designs to be
simulated before being manufactured.
FPGAs are digital integrated circuits (ICs). It contains
programmable(configurable) blocks of logic along with
configurable interconnects between those blocks. “Field
Programmable” portion of FPGA’s name refers to the fact its
programming takes place in the field. It can be customized in
the field like PLDs(programmable logic devices), but can
contain millions of logic gates and used to implement extremely
large and complex functions that previously could be realized
using only ASICs. The significant advantages FPGA over ASIC
is cost-effective.
It is required VHDL codes for designing and Quartus 7.2
software for simulation. BPSK modulation technique is
implemented on Cyclone II family of FPGA devices in this
paper.
II. DIGITAL MODULATION
The process in which some parameters of a periodic
waveform are varied and that signal is used to convey a
message. There are two basic types of modulation: analog
modulation and digital modulation. Generally, if the variation is
continuous according to the input analog signal, the modulation
technique is known as analog modulation. If the variation is
discrete, the modulation is known as digital modulation. Digital
modulation is less complex, more secure and more efficient in
long distant transmission.
In digital communications, the modulation process
corresponds to varying the amplitude, frequency, or phase of the
carrier in accordance with the incoming digital data. There are
three basic digital modulation techniques. They are
- Amplitude-shift keying (ASK) modulation technique,
varying the amplitude of the carrier signal according to
the input data while keeping the phase and frequency
constant,
- Phase-shift keying (PSK) modulation technique, varying
the phase of the carrier signal according to the input data
while keeping the amplitude and frequency constant, and
- Frequency-shift keying (FSK) modulation technique,
varying the frequency of the carrier signal according to
the input data while keeping the amplitude and phase
constant.
There are many other digital modulation techniques used for
different purposes. But only BPSK and BASK modulation
method is used here.
III. BPSK MODULATION SYSTEM
A. Binary Phase-shift Keying (BPSK) Modulation
Technique
The process in which the phase of the sinusoidal carrier
signal is changed according to the message data (“0” or “1”)and
the amplitude and frequency remain constant, is called binary
phase-shift keying (BPSK) modulation technique.
Background equation of BPSK modulation is
st  
2 Eb
cos( 2f ct   )
Tb
where, s(t) = modulated BPSK signal, Eb = transmitted signal
energy per bit, Tb = bit duration (0≤t<Tb) and fc = carrier
frequency.
Figure 1.BPSK Modulation
In figure 1,
s(t )  Eb  (t ) and  (t ) 
2
cos(2f ct ) .
Tb
s1 (t )  Eb  (t )
s2 (t )   Eb  (t )
When the carrier is in phase, 𝛳 is 0˚. So,
st  
2 Eb
cos( 2f ct )
Tb
When the carrier is out of phase, 𝛳 is 180˚. So,
st  
2 Eb
2 Eb
cos( 2f ct   )  
cos( 2f ct )
Tb
Tb
In general, data ‘1’ is assigned to 𝛳 = 0˚ (in phase) and data
‘0’ is assigned to 𝛳 = 180˚ (out of phase). As shown in above,
cosine or sine is used depending on Eb. If ϴ = (π÷2) for data ‘0’
and ϴ = -(π÷2) for data ‘1’, the mo
If ϴ = (π÷2) for data ‘0’ and ϴ = [-(π÷2)] for data ‘1’, the
modulated signal is represented by the following equation.
s(t) = Ac m(t) sin(2πfct)
where, s(t) is BPSK modulated signal, Ac is the amplitude of the
carrier, m(t) is modulating signal and fc(t) is the frequency of
the carrier. The modulation scheme is shown in figure 3.
Figure 2.Basic BPSK Modulator
Figure 6.BASK modulation scheme
If transmitted data is “1”, m(t) = 1. So, s(t) = Ac sin(2πfct).
If transmitted data is “0”, m(t) = -1. So, s(t) = 0.
C. Designing Modulators Using VHDL in Quartus
Software
In this paper, designing and simulation results of BPSK and
BASK modulators using Very High Speed Integrated Circuit
(VHSIC) Hardware Description Language (HDL) are
represented in Quartus software. This design is intended only
for FPGAs (Field Programmable Gate Arrays). The FPGAs are
low-cost effective but are able to function for many applications
with complex operations. Without being programmed, FPGA
cannot do anything. So, a program, which tells the FPGA how
to function, is required. VHDL is capable of controlling how
FPGA must operate. To design electronic devices using FPGAs
with VHDL codes, it is essential not only to know about the
VHDL but also to know the libraries of IEEE and about the
software being used. In this paper, the VHDL codes, which can
transform FPGAs into BPSK and BASK modulators, are
defined for the expected design.
Data generator
clk_data
Figure 3.BPSK modulation scheme
If transmitted data is “1”, m(t) = 1. So, s(t) = Ac sin(2πfct).
If transmitted data is “0”, m(t) = -1. So, s(t) = -Ac sin(2πfct).
Input Source
(clk)
BPSK/BASK
Modulator
Modulated
BPSK signal
B. Binary Amplitude-shift Keying (BASK) Modulation
Technique
The process in which the phase of the sinusoidal carrier
signal is changed according to the message data (“0” or “1”) and
the amplitude and frequency remain constant, is called binary
phase-shift keying (BPSK) modulation technique.
DAC interface
Output data for
DAC
Output data
Figure 7.System Flow Diagram
IV. VHDL FOR BPSK MODULATION SYSTEM
Figure 4.BASK modulation
When the information data is ‘1’, the modulated BASK signal is
st  
2 Eb
cos( 2f ct )
Tb
When the information data is ‘0’,
st   0
In this paper, a data generator, a modulator and an interface
for DAC are designed with VHDL codes. The way how to
define the codes for each one are explained in the followings. At
the top of every code, the libraries, that are defined by IEEE,
must be declared and sometimes, the package created are
declared if they are needed. In this paper, seven codes are
defined to design a modulation system. The codes for BPSK
modulation system are represented in the latter of the paper.
A. Constants
Figure 5.Basic BASK modulators
In the whole process, except DAC interface, the constants
must be used to deal with numbers. So, to assign the constants is
the first of all. In this paper, the package named “constants” has
been created to assign the constants that are needed in the
process of designing. In this code, the constant N is defined for
the length (number of register) of the data generator, the
constant M for the number of positions in the table of the sine
wave’s values (samples), the constant nbits for number of bits of
each word of the table, the constants ndec for number of bits
used as decimals, the constant Pi for the irrational number π and
the constant delta_phi for the phase increment ∆ф between
consecutive positions in the table which is given by (2π/M). The
real constants Pi and delta_phi are used by a function which
initializes the table. The and_vector function is used for
determining the AND logic function of a data vector. Through
the whole process, the “constants” package is declared with the
libraries defined by IEEE at the top of the codes in four codes:
data_gen, real2bit, bask or bpsk, and system. In register1 and
com_dac, it is not declared.
the “clk_bpsk” must be 64 times slower than the input “clk” of
the modulator. To complete a sine wave, 32 sample values are
required. Therefore, the signal “clk_data” must be 32 times
slower than the signal “clk_bpsk. If a reset signal interrupts, the
modulator would initializes variable “count”. The modulated
signal is the sample values of the sine wave table, i.e. in phase,
when data ‘1’ is transmitted, and the modulated signal is
negated the sample values of the sine wave table, i.e. 180˚ out of
phase, when data ‘0’ is transmitted.
B. Data Generator
To define a data generator, the type of the register used in
must be defined first. In this paper, the D register type is used.
The code needed for creating the D register is named as
“register1”. Its function is simple and there are three inputs and
one output here. If preset is ‘1’, the output, Q, is ‘1’ regardless
of the inputs clk and D. If preset is ‘0’, the output Q is the same
as the input D at every rising edge of the input clk.
After the register1 has defined, the main function of the data
generator must be defined. In this process, four D registers are
used to generate data. The VHDL code defined for the function
of the data generator is named as “data_gen”. The first thing to
do is to generate four D registers and “generic” code is used for
this. The sig_xor function is used for the input D and the sync is
for the AND function of the data vector Q_int of all register.
The input reset is mapping to presets of the registers. The data
generator must generated serial data at every rising edge of 4
clock pulses because four registers are used.
Figure 8.Data Generator
C. BPSK Modulator
The codes used in this section are defined for the main
functions of modulator. There are two codes that are defined for
the modulator: the code for the sine wave table named as
“real2bit” and the other for the modulator.
The code, “real2bit”, is a package that is created for the
table used in modulation and there are the values of the samples
of a complete sine wave in this table. The functions of the
package are “truncate” function and “initialize_table” function.
By means of these two functions, the constant “table_wave” can
be created for the sine wave’s samples. The “truncate” function
is able to convert a real number to a binary number of “nbits”
bits in two’s complement notation (“signed” type). After the
“truncate” function, the “initialize_table” saves the sample
values of sine wave in an array of integers with sign (“signed”
type) along the M consecutive positions in the table.
This array of integer with sign is predefined in the package
“constants”. By means of this, the constant named as
“table_wave”, which can give a complete sine wave, is resulted
and it can be indexed to extract its values along the time.
The modulator code is the vital of the whole design because
it controls all to be in synchronization. The input signal “clk” of
the modulator is an undefined clock but it must be the fastest
one, the on-board clock oscillator. The variable “pointer”
indexes the “table_wave”, which contains the sequentially
positioned sample value of the sine wave along the time, at
every rising edge of signal “clk_bpsk. The DAC interface needs
64 clock cycles to finished a complete conversion, and hence,
Figure 9.BPSK modulator
D. BASK Modulator
The same “real2bit” code is used for both modulator in this
research. Only the modulator code is changed. If the
information data to be transmitted is ‘1’, the modulated signal is
the same as the samples of the sine wave table and if data is ‘0’,
the modulated BASK is 0.
Figure 10.BASK modulator
E. DAC Interface
This code is defined as for interface with the DAC (digitalto-analog converter). The code is names as “com_dac”. Three
inputs are defined as clk, reset and data and four outputs as
spi_mosi, spi_sck, dac_cs and dac_clr. The memory of the
interface, named as “memory_dac”, and the variable “count”
play very important roles in this code. The variable “count” is
increased and several conditions are checked on every rising
edge of the input signal “clk”. If “dac_cs” is low logic level and
“count” is equal to 1, the data are loaded to the memory of
interface and “memory_dac” is prepared to transmit the data
towards the selected channel (in this code, data “0000” is
selected in the memory_dac’s address 19-16) through the SPI
bus. The data “0011” from addresses 23-20 is the command
which updates the selected DAC output with the specified data
value, i.e. one or all outputs. The addresses 15-4 in “com_dac”
contain the main data. Other addresses are filled with “don’t
care” bits. After the transmission of 32 bits has finished,
“dac_cs” goes high to indicate that DAC initiates the
conversion. When conversion is done, “dac_cs” goes low again.
Until a reset signal interrupts, this process is repeated endlessly.
If a reset signal appears, it would initialize the interface. The
input “clk” of “com_dac” is the same as “clk_spi” output of the
modulator. The code defines that spi_sck is the inversion of the
input “clk” of the “com_dac” and each bit is transmitted or
received relative to the “spi_sck”. Data is transmitted on the
“spi_mosi”, most significant bit first. This “com_dac” is not the
essential one for the modulation. The block of the “com_dac”
using VHDL in Quartus is shown in the following figure.
In figure 13, the modulated signal is illustrated. When input
data is low, it is 0 (i.e. there is no amplitude) and when input is
high, the modulated signal is the same as the sine wave.
In figures 14 and 15, the outputs of the data generator and
DAC interface are represented respectively.
Figure 11.DAC_interface (com_dac)
F. Integrating Code
A code is required for the integration of three main codes:
data_gen, modulator and com_dac. This integration can be said
port mapping of the whole process. In this paper, the code used
for integration is named as “system”.
The inputs and outputs of the main process are declared in
this entity. In its architecture, bpsk modulator, data_gen and
com_dac are declared as the components because they are the
parts of the whole system. The main functions, port mappings,
are to interconnect the data generator, modulator and DAC
interface. These three mappings make all the things to be
connected and integrated successfully. The “clk_data” output of
the modulator is the “clk” input of the data generator and the
“data” output of the data generator is the “serial_data” input of
the modulator. Mapping all the parts in a system is very
important to run the process successfully.
Figure 14.Simulation of serial_data pin of Data Generator
The figure 7
V. SIMULATION RESULTS
Figure 12 is shown the modulated BPSK signal.
Figure 15.Simulation of outputs of DAC interface
VI. CONCLUSION
Figure 12.Simulation of BPSK modulation
In figure 12, it is shown that the condition of BPSK signal
when the serial_data is changed from low to high. As defined in
the code, the table’s 32 samples are used if serial_data=’1’, and
negated the table’s 32 samples are used if it is ‘0’. The
serial_data is changed from logic level ‘low’ to ‘high’ in the
sixth position of the sample value from the rising edge of the
signal clk_data. Therefore, the sample values of the sine wave is
also changed from the value “100101011010”, the sixth sample
value of sine wave relative to serial_data ‘0’,
to“011010100110”,the sixth value relative to serial_data ‘1’.
The next 7th to 32th sample values of the table relative to input
serial_data ‘1’ will be represented as the parts of the sine wave
unless the data logic level is changed from high to low. When
serial_data goes from high to low, it is happened in the similar
way for the position changing but not for sample values.
By using VHDL on FPGA, the cost effective and high
quality devices can be created. To design a modulator with
VHDL, a package which contains the constants that must be
used, a package which contains the sample values of a complete
sine wave, and a modulator code are required. In this paper, the
codes for data generator and DAC interface are developed to
perform a complete process. The code to integrate all the codes
is also important. The purpose of this paper is to design BPSK
and BASK modulator by using VHDL.
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Figure 13.Simulation of BASK modulation
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