A Column Parallel ADC With Digital And Analog CDS
For Low Noise CMOS Image Sensor
Abstract: Column parallel ADCs are widely used in high speed low noise CMOS image sensors.
This paper presents a column parallel ADC with digital and analog CDS which has advantages of
dual-CDS, simple structure and low noise. Analog CDS used in comparator eliminates the offset
of the comparator and the pixel output that causes FPN. CDS in digital domain has been chosen to
cut down the design work of analog circuit, so the noise and the power consumption in analog
circuit could be reduced. A 12bit up/down ripple counter which consists of 11 D flip-flops is
designed to achieve digital CDS.
Key words: column parallel ADC, digital and analog CDS, CMOS image sensor
1. Introduction
Compared with CCD image sensor, the CMOS image sensor has advantages of low power
consumption, low noise, large dynamic range and low cost. CIS are widely used in digital camera,
scanner, safety intendance, military spy and space observation. ADC, which converts the analog
signal from active pixels to digital signal, is the linker of analog and digital circuit. The
performance of ADC may directly influence the image quality of the CIS, so ADC is the core of
the signal readout circuit. Considering about high speed and large array pixels, column parallel
ADC is proven to be one of better choices. Column parallel ADCs allow for low bandwidth
readouts, and have the advantages of low power consumption and small area.
Nowadays column parallel ADCs usually used are single-slope ADC, ∑Δ ADC, SAR ADC
and cyclic ADC. SS ADC is simple and small, but its speed is usually insufficient when the frame
rate of the sensor is high. The resolution of ∑Δ ADC is high, but the speed and power
consumption could not meet the requirement. SAR ADC requires a high precision internal DAC,
and it is difficult to achieve more than 10-bit resolution in column. Cyclic ADC has a better
linearity, but requires sub-DAC and many capacitances that make the area too large.
The column parallel ADC we designed is imitated to the architect in literature [] as figure 1
shows. In this ADC architect, analog and digital CDS are used to eliminate the offset and the
column fixed-pattern noise (FPN). Commonly analog circuit design should cost more time and
should be more difficult than digital circuit design. Digital CDS is used in the column parallel
ADC so that the design work of analog circuit could be cut down and the noise in analog circuit
would be reduced, as well as the power consumption.
Figure 1: the architecture of column parallel ADC
2. Analysis
2.1 analog CDS
CDS in analog domain is usually used in column parallel ADCs, and some ADCs integrate
offset cancellation circuit to reduce the column fixed-pattern noise (FPN). Commonly the circuit
used in CDS is sample and hold circuit as figure 2 shows. In sample stage when S1=1 and Vin =
Vsig , considering Vos of amplifier,
VC1 =
A
A
Vref +
V − Vsig , VC2 = 0
A+1
A + 1 os
In hold stage when S1=0 and Vin = Vrst,
,
VC1
= Vref −
Vout
A
,
+ Vos − Vrst , VC2 = Vref −
A+1
A
Vout + Vos
During the two stages the charge in X would not be changed,
,
,
VC1 C1 + VC2 C2 = VC1 C1 + VC2 C2
If the amplifier gain is infinite, we could get
C1
Vout = Vref + Vos − (Vrst − Vsig )
C2
So by CDS, we could subtract Vsig from Vrst and eliminate the FPN in the column bus, but
Vos could not be eliminated. It could cause FPN in output port and influence the image quality.
Figure 2: double sampling circuit
The analog CDS in our ADC is in the part of comparator. Figure 3 shows the two work stages
of the comparator (Vf is the pixel output that causes FPN). In stage (a) the switch is closed and
Vin = Vf
Q = Vf C.
In stage (b) the switch is open and the charge of capacitance is not changed,
Vin = Vx + Vf
Q = (Vx + Vf − V− )C = Vf C.
We could get
V− = Vx
Vout = −AVx.
During the analog CDS, the output which causes FPN is eliminated. By the way, the offset
of the amplifier could also be eliminated.
Figure 3: comparator and the two work stages
2.2 digital CDS
The digital CDS is finished in the part of up/down ripple counter. Figure 4 shows the work
mode of the ripple counter. In the down counting period the reset signal Vrst is converted to
binary number and then the counter is set to up counting mode. So in the up counting period the
counter could digitally subtract the conversion of the sensor signal from the reset signal after the
charge transfer from the photodiode. The FPN in input signals is eliminated by CDS. By the way,
the error caused by transfer delay and finite gain of the comparator could also be eliminated by the
two counting period so that the requirement of the comparator could be cut down. This reduces the
design work of analog circuit and the noise in analog circuit would be decreased, as well as the
power consumption.
Figure 4: work mode of the up/down ripple counter
By using dual CDS, the analog pixel signal is converted to the corrected digital output signal
in the individual columns in parallel. When the dual CDS is finished, the digital data is transferred
to the column latches included in each ripple counter block. This pipelines the AD conversion and
horizontal data transfer.
3. Circuit design
3.1 comparator
The basic function of comparator is to compare two analog signals and export a binary signal
through the result of comparison. Usually a comparator consists of two sections: pre-amplifier and
latch. The latch stage is used to separate Vout and Vin of the comparator so that the kickback
noise could be eliminated. Figure 5 shows the comparator we used.
Figure 5: comparator
The main factors which influence the speed and precision of the comparator are the finite
gain of OTA, the input offset voltage and the charge injection of the switch. The switch is used to
achieve analog CDS and the offset of the OTA could be cancelled as well. Figure 6 shows the two
steps of the comparator. In step (a) the switch is closed. At this time,
Vout = Vos
Q = −Vos C
In step (b) the switch is opened. At this time, the charge of capacitance is not changed. We
could get
(Vin − V− )C = −Vos C
V− = Vin + Vos
Vout = A(Vos − V− ) = −AVin
Figure 6: two steps of comparator
If the parasitic capacitance Cin is considered,
−Vos (C + Cin ) = (Vin − V− )C − V− Cin
C
V− =
V + Vos
C + Cin in
Vout = A(Vos − V− ) = −A
C
V
C + Cin in
It is proven that Cin makes Vout decrease compared to the ideal Vout . So we should cut
down Cin if possible. The charge injection of the switch is another critical factor. So we use
CMOS switch to lower the influence of charge injection.
By using digital CDS, the little offset and error could be eliminated by digital circuit, so the
requirement of the comparator could be cut down. The OTA in comparator do not need high gain
so that we choose simple differential amplifier which is low power consumption and low noise
(Figure 7).
Figure 7: OTA in comparator
In order to reduce 1⁄f noise, we choose PMOS as input port. If 1⁄f noise is ignored and the
current of M0 is ISS , the equivalent input noise of the OTA could be
8kTγ
gm3
2 =
̅̅̅̅
Vin
(1 +
)
gm1
gm1
ISS
⁄V ∗
8kTγ
3
=
(1 +
)
ISS
gm1
⁄V ∗
1
=
8kTγ
V1∗
(1 + ∗ )
gm1
V3
V ∗ is the over drive voltage of the transistors and γ would change when the channel length
changes.
3.2 12bit up/down ripple counter
The up/down ripple counter is the most critical part of the column parallel ADC. It is made of
two parts: 1) up/down ripple counter, which is used to achieve digital CDS; 2) latch stage, which
is used to hold and export the result from the counter.
Figure 8 shows the up/down ripple counter which we use. We regard the output of latch as
the first bit of the counter so that it equals the counter counting two numbers every clock cycle. In
this way we only need 11 D flip-flops to achieve 12bit ripple counter. In the ripple counter, MUXs
are equal to clock selectors. When the control signal φUD is low, the counter is in down counting
period; when φUD is high, the counter transfers to up counting mode. We also add a control
signal φlock in the up/down ripple counter to hold the counter result. When φlock is high, the
counter would hold the current result. When φlock is low, the counter would transfer to counting
mode. The reset control signal φrst is not signed in the figure.
Figure 8: up/down ripple counter
The latch stage is quite simple which consists of a latch and a selection transfer gate. In order
to make ADC applied to large array pixels, we design two selection stages.
Figure 9 shows the work timing of the up/down ripple counter. During reset signal counting
period, the counter is in up counting mode. When φlock is low, the result of the counter would
not change. The reset signal Vrst is converted to binary x. After φUD changes to high level, the
counter transfers to down counting mode. During sensor signal counting period, the counter will
digitally subtract the conversion of the sensor signal from the reset signal. After the sensor signal
counting finished, the corrected sensor signal Vsig is converted to binary q and the digital CDS is
finished. The counter result q would be saved in latch stage transferred to qb through a latch.
Then when the two stages column selection signal——lsel_en and col_sel are high level, the
result qb will be readout.
Figure 9: timing of up/down ripple counter
4. Experimental results
4.1 comparator
Noise analysis
4.2 ADC