CHAPTER
DIGITAL ARITHMETIC
6.0 INTRODUCTION
In this chapter you will study digital arithmetic. Digital arithmetic is
used in the internal calculations performed in many modern
computer systems. You will learn about arithmetic using binary,
hexadecimal, and BCD numbers. Circuits to perform digital
arithmetic will be constructed and their operation analyzed.
Upon completion of this chapter you should be able to:
• Understand
binary
unsigned numbers.
addition
with signed and
• Use the two's complement form of binary numbers to
perform arithmetic.
• Multiply and divide binary numbers.
• Perform arithmetic operations on BCD and hexadecimal
numbers.
• Implement digital arithmetic circuits.
6.1 OBJECTIVES
6.2 DISCUSSION
Until this chapter, the numbers you have studied have been positive
integers or fractions. In fact when we say that an N bit binary number
can have a count of 2N - 1 we are implying that such a number is
positive and uses all of the bits to express magnitude. Realize that
this convention is arbitrary and that some of the bits can be used to
indicate qualities other than magnitude.
6.2.0 Binary Addition
FIGURE 6-1. Rules of
Binary Addition.
The positive binary integers used until now can be added a bit
at a time by following a few simple rules which are shown in Figure
6-1.
0 + 0 = 0 1 + 0 = 0 + 1 = 1 and
1 + 1 = 0 with a carry of 1
These rules are straight forward. Notice that the only
operation resulting in a nonzero carry is the addition of two ones.
6.2.1 Signed
Numbers
FIGURE 6-2. Example of
Signed Numbers.
While the numbers used to this point are fine for counting,
they have not allowed representation of negative quantity. Since
numbers can be negative or positive, a single bit can be used to
indicate the sign of a number while the remaining bits are used to
indicate the magnitude of the number. The convention normally
adopted is to have the MSB used for the sign bit and to have a zero
in the sign bit indicate a positive number. This concept is illustrated
in Figure 6-2.
01010111 = 87
11010111 =-87
The rules used for addition will still work with these numbers.
Some additional rules are needed to handle the sign bits. These
rules are summarized below.
A.
To add numbers with like signs add the magnitudes and use
the common sign in the sign bit.
B.
To add numbers with unlike signs find the difference in
magnitude and use the sign of the number with the greatest
magnitude.
Subtraction can also be accomplished with signed binary
numbers in the same manner as is done with the decimal numbers.
To subtract we merely change the sign of the subtrahend then add
the subtrahend to the minuend following the rules of binary addition
of signed numbers. Subtraction can also be carried out directly as
with decimal numbers. The rules for binary subtraction are shown in
Figure 6-3.
1-1=0
1-0 = 1
0-0 = 0
FIGURE 6-3. Rules for Binary
Subtraction.
0 - 1 = 1 WITH A BORROW OF 2 FROM THE NEXT HIGHER
BIT
Notice that the borrow in binary is a 2 instead of a ten as you
are familiar with when using decimal numbers.
A special form of writing numbers known as complement
notation is used widely for binary arithmetic. This usage has become
common because the complement form of a binary number is easily
represented and manipulated by digital machines. The formula for
the radix complement of a number is : Rn-N where R is the radix, n is
the number of digits in the word representing the number and N is the
number to be complemented. The radix-minus-1 complement is
formed by subtracting one from the radix complement. Since you are
concerned with binary numbers for use with computers, you will use
the two's complement for the radix complement and the one's
complement as the radix-minus-1 complement. Examples of these
complements are shown in Figure 6-4.
NUMBER:
01010101
ONE'S COMPLEMENT:
00101010
10100100
TWO'S COMPLEMENT:
00101011
10100101
6.2.2 Complement
Notation
11011011
FIGURE 6-4. Examples of
Complement Notation.
The left number is decimal + 85 and the right number is decimal
- 91. Notice that the left most bits, the sign bits, are not changed by
either of the complement operations. Also note that the one's
complement is the complement of the bits of the magnitude with the
sign bit retained.
This means that the hardware to form the one's complement is
simply an inverter for each of the magnitude bits. The two's
complement can be formed by adding one to the one's complement.
This can be done using an EXOR gate and some additional circuitry.
Subtraction of binary numbers is frequently performed by adding the
two's complement of the subtrahend to the minuend. This process is
illustrated in Figure 6-5.
DECIMAL
FIGURE 6-5. Subtraction
Using Two's Complement
Notation.
BINARY
14
00001110
-5
+ 11111011
9
100001001
Notice that the result of the subtraction has an overflow or
carry bit. The result also will be in a signed magnitude format with
negative numbers represented as two's complements. The carry bit
is not used in this example hence it is discarded.
6.2.3 Binary
Multiplication
The process for multiplying binary numbers is similar to the
process used to multiply decimal numbers. Multiplication is
accomplished by successive addition. For example 6 x 3 = 6 + 6
+ 6. When multiple digit decimal numbers are multiplied, the digits
of the multiplier are used one at a time to operate on the
multiplicand. The partial products, which are the result of these
operations, are added to form the final product. Each partial product
is shifted one place to the left as the multiplicand digits
are used from LSB to MSB. This has the effect of multiplying each
partial product by ten. A similar set of rules is used in binary
multiplication. Binary multiplication is simpler since only two results
can be obtained. The rules for binary multiplication are:
A. When a binary number is multiplied by one the result is the
original number or multiplicand.
B.
When a binary number is multiplied by zero the result is zero.
An example of multiplying a multi-digit binary number is shown
in Figure 6-6.
1101 MULTIPLICAND
X 101 MULTIPLIER
1101
PARTIAL PRODUCTS
0000 + 1101
1000001
FIGURE 6-6. Example of
Multi-Digit Binary
Multiplication.
FINAL PRODUCT
This method of multiplying will give correct answers and is very
similar to the one you use to multiply decimal numbers. This is not
the only way to perform binary multiplication nor is it the most
hardware efficient. The same result can be obtained by shifting the
previous result to the right instead of shifting each successive partial
product to the left. This method is shown in Figure 6-7.
1101 MULTIPLICAND
X 101 MULTIPLIER
1101
00000
001101
1000001
INTERMEDIATE RESULTS
NOTE: ONLY THE LAST
TWO TERMS ARE SUMMED!!
FINAL PRODUCT
FIGURE 6-7. Alternate
Method for Multiplying
Binary Numbers.
This method of multiplication will also give correct results.
Notice that for a zero bit in the multiplier the intermediate result is
shifted right one position. For a one bit in the multiplier the
intermediate result is shifted right one bit then the multiplicand is
added to the result.
This method of multiplying is more hardware efficient in that it
can be implemented using one fewer registers than would be
required to implement the method shown in Figure 6-6.
6.2.4 Binary Division
Binary division can be accomplished by successive binary
subtraction. This method will give accurate results but is slow and
cumbersome for division of large numbers. The number of steps
required to perform the division can be reduced by a process called
shifting. An example of this process applied to decimal numbers is
shown in Figure 6-8.
QUOTIENT 1500/5
We know that the farthest that 5 can be shifted and still be
divided into 1500 with an integer result is two places, so 500 will be
used for this process.
FIGURE 6-8. Alternate
Method for Division.
1500
-500
100 PARTIAL QUOTIENT
1000
-500
500
100 PARTIAL QUOTIENT
-500
0
300
100 PARTIAL QUOTIENT
FINAL QUOTIENT
This same principle can be applied to binary division. This
method is frequently used in computer arithmetic. It can be
implemented using subtraction circuitry in conjunction with some
logic to determine the size of the number to be subtracted from the
dividend. An example of this method, known as the restoring method,
applied to binary numbers is shown in Figure 6-9.
The quotient is 1000001/1101
1000001 can at least be divided by 110100 so,
-110100
1101
-1101
FIGURE 6-9. Binary Division by
the Restoring Method.
add 100 to quotient
use 1101 for division
0
add 1 to complete quotient
quotient = 101
You could use a system of addition and subtraction using
fifteens and sixteens complement notation for hexadecimal
arithmetic. However, with the large number of binary arithmetic
devices available it is easier to convert from hexadecimal to binary
for performing arithmetic. When this is done, all answers will have to
be converted back to hexadecimal after computation.
BCD addition is frequently used in systems where the results
are displayed as decimal numbers. Calculators are one example of
this type of system. You have already learned about BCD notation.
Some interesting things happen with BCD arithmetic because of the
6 unused states in a BCD digit. Figure 6-10 illustrates BCD addition
problems.
6.2.5 Hexadecimal
Arithmetic
6.2.6 BCD Addition
DECIMAL BCD
3 0011
+4
7
FIGURE 6-10. BCD
Addition Examples.
+ 0100
0111
CORRECT RESULT
FIGURE 6-10.
Continued.
6 0110
+1000
+8
14
1110
INCORRECT RESULT,
NO CARRY
9 1001
+8
+100
0
17
0001 0001
WRONG RESULT,
CARRY GENERATED
This problem occurs because the carry for the decimal system
occurs for sums greater than nine while the carry in the BCD system
occurs for numbers greater than 15. To correct this, a six must be
added to all sums greater than nine. To do this a machine would need
to be able to recognize results of sums which are greater than nine
and add six to those sums. Results of sums less than nine are correct
in BCD arithmetic.
6.2.7 The Half-adder
FIGURE 6-11. Half-Adder.
Until now you have concentrated on the mechanics of binary
related arithmetic and we have only hinted at how to use digital
circuits to perform arithmetic operations. The next few sections will
concentrate on implementing arithmetic circuits.
Your study of arithmetic circuits will begin with the binary
half-adder. The schematic and truth table for the half-adder are
shown in Figure 6-11.
Notice that this circuit has two inputs and two outputs. The
EXOR gate performs the addition while the AND gate detects when
both inputs are ONE and forms the carry output. This circuit is called a
half-adder because it lacks the ability to accept a carry input from a
previous addition.
The full-adder has three inputs and two outputs. The inputs are
the two bits to be added and a carry input from a previous addition.
The full-adder has the sum and carry outputs. The schematic and
truth table for the full-adder are shown in Figure 6-12.
6.2.8 Full-adder
FIGURE 6-12. Full-Adder.
A parallel binary adder will perform the addition operation on
multiple bit binary numbers. The circuit which performs the function in
the TTL logic family is the 7483. The circuit has some features that
require discussion.
The 7483 is a four-bit binary adder with fast carry. The fast carry
is made possible by circuitry which is called a "look ahead" carry
circuit. This circuitry samples the output of each individual adder thus
saving the time required for a carry to ripple through each adder
stage. The 7483 also performs math in the true logical sense. This
means that outputs will all be true. For one's complement arithmetic
this means that the end around carry can be directly implemented.
An End Around
6.2.9 Parallel Binary
Adder
Carry or EAC is needed when the result of the addition of two
numbers with unlike signs is positive ( >0). The block diagram for
the 7483 is shown in Figure 6-13.
FIGURE 6-13. Parallel
Adder IC.
6.2.10 BCD Adder
A BCD adder can be formed from two four-bit adders and
some additional circuitry. The schematic for a BCD adder is
shown in Figure 6-14.
FIGURE 6-14. BCD Adder
Circuit.
Notice that the first adder performs the basic addition,
while the second adder will add six to outputs that are nine or
greater. The second adder is controlled by the AND and OR
gates which detect when the output of the main adder is nine or
greater.
A reasonable variety of IC multipliers are available in the TTL
logic family. A dedicated multiplier is generally used only where
speed is very important. An example of this type of circuit is the
74LS261, a two-bit by four-bit binary multiplier, capable of producing
a five-bit output in 26 nS. Where speed is less of a consideration an
Arithmetic Logic Unit or ALU is frequently used.
These devices can be used to perform the multiplication
function and other arithmetic and logic functions. The 74LS181 is an
example of an ALU. It performs arithmetic and logic operations on
two four-bit binary numbers.
In this chapter you have learned about binary arithmetic and the
circuits required to perform binary arithmetic. You have learned
about the half- and full-adders, binary multipliers, BCD adders, and
ALUs as means of performing binary arithmetic. These items form
the backbone of digital arithmetic computation.
1.
6.2.11 Binary
Multipliers
6.3 SUMMARY
What is the sum of 101 and 011 ?
6.4 REVIEW
QUESTION
S
2.
Compute the difference between Oil and 010.
3.
What is meant by a half-adder ?
4.
Divide 111001 by 10010.
5.
Multiply 101 by 110.
6.
Convert FF hexadecimal to binary.
7.
Convert FF hexadecimal to decimal.
8.
What is an ALU ?
9.
Write -120 in the two's complement binary format.
10.
Write -120 in the one's complement binary format.
11.
What is the range of signed number in an eight-bit register
using two's complement notation ?
12.
Convert 120 to BCD.
In this lab exercise you will learn to implement binary adders. You
will learn about the half-adder and the full-adder.
LAB EXERCISE 6.1
Binary Adders
Objectives
C.A.D.E.T.
Materials
74LS86QuadEXORIC
74LS08 Quad AND IC
74LS32 QUAD OR IC
Jumper Wires TTL
Data Book
1.
2.
6-15.
You will use a 74LS08 and a 74LS86 for the first part of
this experiment. Place both of these ICs on the C.A.D.E.T.
breadboard and wire power to them.
Procedure
Wire the circuit shown in Figure
FIGURE
6-15.
Schematic.
3.
Switch LSI and LS2 to their LOW positions. Turn on
powei
4.
Use LSI and LS2 for the A and B inputs. Use LI1 and LI2 to
observe the sum and carry outputs. Record the truth table for
this circuit.
5.
Turn off power.
Half-Adder
6.
Add a 74LS32 IC to the C.A.D.E.T. breadboard. Wire power
and ground to this circuit.
7.
Wire the circuit shown in Figure 6-16.
FIGURE 6-16. Full-Adder
Schematic.
Questions
8.
Switch LSI, LS2, and LS3 to LOW. Turn on power.
9.
Use LSI, LS2 and LS3 for the A, B and Carry in inputs. Use LI1
and LI2 to observe the sum and carry outputs. Record your
observations in the form of a truth table.
1.
Explain the difference between a half-adder and a full-adder.
------------------------------------ * ---------------------------------------2.
LAB EXERCISE 6.2
Parallel Binary Adder
Objectives
118
Use the truth table from step 9 to form the logic equations and
Karnaugh maps for the full-adder.
In this lab exercise you will learn about the 4-bit parallel IC adder. You
will use this adder to perform one's complement arithmetic.
C.A.D.E.T.
Materials
7483 4-Bit Binary Full-Adder With Fast Carry
74LS86 Quad Two Input EXOR Gate Jumper
Wires TTL Data Book
1.
2.
You will use the 74LS86, and 7483 ICs for this lab. Insert
both of these ICs in the breadboard and wire the power and
ground to both ICs. Be particularly careful with the 7483 as it
has the power on pin 5 and ground on pin twelve of the 16
pin DIP.
Procedure
Wire the circuit shown in Figure 6-17.
FIGURE 6-17. Parallel
Binary Adder Circuit.
3. This circuit requires some explanation. The four gates of the
74LS86 are used to form a true/complement circuit. This
will allow you to add numbers with unlike signs.
4.
This circuit is connected so that the inputs act as unsigned
magnitudes. Use LS1-LS4 as the A1-A4 inputs, LS5-LS8 as
the B1-B4 inputs, LI1-LI4 as the sum output, and LI8 as the
carry output. Observe this circuit and describe its operation.
5.
Now you will configure this circuit for subtraction. Remove
the wire connecting pins 2,5,9 and 13 of the 74LS86 to
ground at the ground end.
6.
Connect this wire to +5V. This will enable the complement
output of the true/complement gate.
7.
Remove the jumper between pin 13 of the 7483 and ground.
Connect this jumper wire to pins 13 and 14 of the 7483. This
change will perform the end-around carry needed for one's
complement arithmetic.
8.
Switch all logic switches to LOW. Turn on power and recorc
your observations. Use the same inputs and outputs as step
5. Do not change the LS5=LS8 inputs at this time. Remembe
that the inputs on LS1-LS4 are entered into the adder in a
one's complement format.
9.
Use the LS5-LS8 switches as the input for the minuend whil
LS1-LS4 are used as the subtrahend. Describe the action of
this circuit.
1. Describe the two different types of adders used in this laboratory.
Questions
2.
Show two ways that the 7483 can represent a 0 when
connected as a one's complement subtractor.
3.
What changes would have to be made to the circuit of step 8
for the circuit to add two positive binary numbers?
In this lab exercise you will learn about the BCD adder. You will
construct a BCD adder and observe it's operation.
LAB EXERCISE 6.3
The BCD Adder
Objectives Materials
C.A.D.E.T.
7483 4-Bit Adder (2)
74LS27 Triple Three Input NOR
74LS04 Hex Inverter
74LS08 Quad AND
Jumper Wires
TTL Data Book
Procedure
1.
Place two 7483s, a 74LS08, a 74LS27, a 74LS04, a 7447,
and a LTS312 on the breadboard and wire power and ground
to them.
2.
Wire the circuit shown in Figure 6-18A.
3.
Switch all logic switches to LO.
4.
Use LS1-LS4 as one adder input and LS5-LS8 as the other
adder input. LI8 indicates a carry while LI1-LI4 indicate the sum
output. Add several numbers and record your observations.
5.
Turn off power. Remove the wires from LI-L4 and connect them
to pins 7,1,2, and 6 of a 7447 as shown in Figure 6-18B.
Remove the wires from L7 and L8 and connect them to pins 1
and 2 of the74LS27. Wire pin 13 of the 74LS27 to ground. Wire
pin 12 of the 74LS27 to pin 3 of the 74LS04. Wire pin 4 of the
74LS04 to LED 1 as seen in Figure 6-18B.
6.
Switch all logic switches to LO. Turn on power. Now use the
same inputs as step 4 but this time use LED 1 and the seven
segment display as outputs. Again observe the adder operation
and record your observations.
1.
What are the results when a number greater than 20 is the sum Questions
output for the circuit of step 6 ?
2.
What does the circuitry added to pins 1 and 2 of the 74LS27 in
step 5 do ?
LAB EXERCISE 6.4
In this lab exercise you will study the Arithmetic Logic Unit or ALU. You
The ALU
will use the ALU to perform binary multiplication and subtraction.
Objectives
Materials
C.A.D.E.T.
74181 Arithmetic Logic Unit
Jumper Wires TTL Data
Book
Procedure
FIGURE 6-19. 74181 Adder.
The 74181 ALU is the largest and most complex IC you have
used to date. The 74181 performs a variety of arithmetic and logic
functions on two four-bit inputs. It provides a four-bit with carry output.
It has a carry input and is controlled by the
LS1-LS4, and M inputs. The A and B inputs and the F output can be
used as either true or complement bits. For this reason you will often
find two function tables for the 74181 listed in data books.
1.
Place the 74181 on the breadboard and wire power and
ground to it.
2.
Wire the circuit shown in Figure 6-19.
3.
Switch all logic switches to LOW. Turn on power. Use LS1-LS4
as the A input, LS5-LS8 as the B input, LI1-LI4 as the F output
and LI8 as the carry output. Observe and describe the action of
this circuit. Remember that the carry output is LO true.
4.
The 74181 can perform a variety of other functions. The type
of function performed is controlled by the M input,
while the function selection is via the LS1-LS4 inputs. Turn off
power.
5.
You will now change the function selection. Remove the
wiring to pins 3-6. Wire pins 3 and 6 to ground and pins 4 and
5 to +5V. Place all logic switches off.
6.
Use the same inputs and outputs as before. Observe the
circuit's operation and describe it. Pay particular attention to
incorrect arithmetic results.
7.
Turn off power.
8.
Turn on power and observe the circuit's operation. Describe
the results. Again look for any incorrect outputs for arithmetic
operations.
Wire pin 7 to ground.
Questions
1.
What circuitry would be needed to perform an end around
carry for the circuit of step 6 ?