IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
S. NO
CODE
TITLE
KEYWORDS
YEAR
High-Throughput Multi standard Transform Core Multi standard
Supporting MPEG/H.264/VC-1 Using Common transform CSDA,
Sharing Distributed Arithmetic
Image & Video
compression, DCT
Improved 8-Point Approximate DCT for Image Approximate DCT,
and Video Compression Requiring Only 14 low-complexity
Additions
algorithms, image
compression, Video
Compression, HEVC
Area-efficient, CSLA,
Area-Delay Efficient Binary Adders in QCA
Application-specific
integrated circuit
(ASIC),
Area–Delay–Power Efficient Carry-Select Adder
Adder, arithmetic
unit, low-power
design
2014
1PVL-05
Input Vector Monitoring Concurrent
Architecture Using SRAM Cells
2014
6.
1PVL-06
7.
1PVL-07
8.
1PVL-08
9.
1PVL-09
10.
1PVL-10
Simplifying clock gating logic by matching Clock gating, gating
Factored forms
logic factored form,
factoring tree
Data encoding techniques for reducing energy Data encoding,
Consumption in network-on-chip
interconnection on
chip, low power,
network-on-chip
Area-Delay-Power Efficient Fixed-Point LMS Adaptive filters, least
Adaptive Filter With Low Adaptation-Delay
mean square
algorithms, fixedpoint Arithmetic
Analysis and Design of a Low-Voltage Low- Double-tail
Power Double-Tail Comparator
comparator, dynamic
clocked comparator,
High-speed ADC
converters, low-power
analog design
Fast Sign Detection Algorithm for the RNS Computer arithmetic,
Moduli Set {2n+1 − 1, 2n − 1, 2n}
residue number
system (RNS),
1.
1PVL-01
2.
1PVL-02
3.
1PVL-03
4.
1PVL-04
5.
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
BIST Built-in self-test,
design for testability,
testing
2014
2014
2014
2014
2014
2014
2014
2014
WEB SITE : http://www.1pointer.com
IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
restricted moduli set,
sign detection.
Efficient Integer DCT Architectures for HEVC
High Efficiency
Video Coding
(HEVC), integer
discrete cosine
transform (DCT),
video coding, DCT,
H.265
Bit-Level Optimization of Adder-Trees for Adder-tree
Multiple Constant Multiplications for Efficient optimization, finite
FIR Filter Implementation
impulse response
Filter, multiple
constant
multiplication, FIR,
MCM
11.
1PVL-11
12.
1PVL-12
13.
1PVL-13
Design of Efficient Binary Comparators in Binary comparators,
Quantum-Dot Cellular Automata
majority gates
2014
14.
1PVL-14
2014
15.
1PVL-15
16.
1PVL-16
17.
1PVL-17
18.
1PVL-18
Reverse Converter Design via Parallel-Prefix Digital arithmetic,
Adders: Novel Components, Methodology, and parallel-prefix adder,
Implementations
residue number
system (RNS), reverse
converter.
Low-Complexity Low-Latency Architecture for Data comparison,
Matching of Data Encoded With Hard Systematic ECC, Hamming
Error-Correcting Codes
distance, tag
matching, systematic
codes
Multifunction
Residue
Architectures
for Computer arithmetic
Cryptography
Montgomery
multiplication,
parallel arithmetic &
logic Structures
Defense Against Primary User Emulation Attacks Network security,
in Cognitive Radio Networks Using Advanced primary user
Encryption Standard
emulation attacks,
secures spectrum
sensing, dynamic
spectrum Access, and
eight-level vestigial
sideband
Aging-Aware Reliable Multiplier Design With Adaptive hold logic
Adaptive Hold Logic
(AHL), negative bias
temperature
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
2014
2014
2014
2014
2014
2014
WEB SITE : http://www.1pointer.com
IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
Instability, positive
bias temperature
instability, reliable
multiplier, variable
latency
Critical-Path Analysis and Low-Complexity Adaptive filters,
Implementation of the LMS Adaptive Algorithm
critical-path
optimization, least
mean square
algorithms, LMS
adaptive filter
19.
1PVL-19
20.
1PVL-20
Eliminating Synchronization
Sequenced Latching
21.
1PVL-21
22.
1PVL-22
Precise VLSI Architecture for AI Based 1-D/ 2-D
Daub-6 Wavelet Filter Banks With Low AdderCount
Gate Mapping Automation for Asynchronous
NULL Convention Logic Circuits
23.
1PVL-23
24.
1PVL-24
25.
1PVL-25
Latency
Using Duplication, latency,
metastability,
speculation,
synchronization
2014
2014
AI encoding, errorfree algorithm,
Daubechies wavelets
Gate mapping,
Automation, NULL
convention logic
(NCL),factoring,
grouping, technology
mapping
Efficient FPGA and ASIC Realizations of DA- Finite impulse
Based Reconfigurable FIR Digital Filter
response filter,
reconfigurable
implementation,
circuit optimization
distributed arithmetic
Non binary LDPC Decoder Based on Simplified ECC, Hardware
Enhanced Generalized Bit-Flipping Algorithm
architecture, iterative
decoding, nonbinary
low-density paritycheck codes, Symbol
flipping
Decoding
2014
Efficient Algorithm and Architecture for Elliptic Crypto-processor,
Curve Cryptography for Extremely Constrained Gaussian normal basis
Secure Applications
(GNB), Koblitz
curves, point
multiplication, RFID,
security, wireless
2014
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
2014
2014
2014
WEB SITE : http://www.1pointer.com
IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
sensor networks
26.
1PVL-26
An Optimized Modified Booth Recoder for Add-Multiply
Efficient Design of the Add-Multiply Operator
operation, arithmetic
circuits,
Modified Booth
recoding,
2014
27.
1PVL-27
Efficient VLSI Implementation of Neural Hyperbolic tangent,
Networks With Hyperbolic Tangent Activation neural networks,
Function
nonlinear
activation function
2014
28.
1PVL-28
2014
29.
1PVL-29
30.
1PVL-30
31.
1PVL-31
Recursive Approach to the Design of a Parallel Binary adders ,
Self-Timed Adder
CMOS design,
Asynchronous
circuits, Digital
arithmetic
Design of Digit-Serial FIR Filters: Algorithms, digit-serial arithmetic,
Architectures, and a CAD Tool
finite impulse
response (FIR) filters,
multiple constant
multiplications
Parallel AES Encryption Engines for Many-Core Advanced encryption
Processor Arrays
standard (AES),
parallel processor,
software, fine-grained
Design of Testable Reversible Sequential Circuits Cellular automata,
Fredkin
gate, conservative
logic,
quantum-dot,
reversible logic
32.
1PVL-32
Test Patterns of Multiple SIC Vectors: Theory and Built-in self-test
Application in BIST Schemes
(BIST), low power,
single-input
Change (SIC), test
pattern generator
(TPG).
2013
33.
1PVL-33
A Novel Modulo Adder for 2n-2k- 1Residue Carry correction,
Number System
modular adder,
parallel prefix,
Residue number
system (RNS), VLSI.
2013
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
2013
2013
2013
WEB SITE : http://www.1pointer.com
IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
Improvement of the Security of ZigBee by a New Chaos cryptosystem,
Chaotic Algorithm
encryption, RFCA,
security, ZigBee
CORDIC Based Fast Radix-2 DCT Algorithm
Coordinate rotation
digital computer, fast
radix-2 algorithm,
DCT
Radix 6, Discrete
Split Radix Algorithm for Length 6mDFT
Fourier transforms,
fast Fourier transform
(FFT), general split
radix
Low-Complexity Multiplier for GF(2m) Based on All-one polynomial,
All-One Polynomials
finite field, systolic
design
2013
1PVL-38
Low-Power, High-Throughput, and Low-Area Adaptive filter,
Adaptive FIR Filter Based on Distributed distributed
Arithmetic
arithmetic (DA), least
mean square
algorithm
2013
39.
1PVL-39
Multicarrier Systems Based
Layered IFFT Structure
2013
40.
1PVL-40
41.
1PVL-41
42.
1PVL-42
43.
1PVL-43
Design of an Error Detection and Data Recovery Data recovery, error
Architecture for Motion Estimation Testing detection, motion
Applications
estimation, residueand-quotient (RQ)
code
Period Extension and Randomness Enhancement Chaotic map, mixing,
Using High-Throughput Reseeding-Mixing PRNG period extension,
pseudo random
number generator
(PRNG), reseeding
Area-Efficient Parallel FIR Digital Filter DSP, FIR algorithms,
Structures for Symmetric Convolutions Based on parallel FIR,
Fast FIR Algorithm
symmetric
convolution
Measurement and Evaluation of Power Analysis Null convention logic
Attacks on Asynchronous S-Box
(NCL), Security, Side
channel attack (SCA),
substitution box (SBox)
34.
1PVL-34
35.
1PVL-35
36.
1PVL-36
37.
1PVL-37
38.
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
on
Multistage IFFT, multicarrier
systems
2013
2013
2013
2012
2012
2012
2012
WEB SITE : http://www.1pointer.com
IEEE PROJECTS TITLES 2014-2015
VLSI
Branch Off: Chacko Towers, Anna Nagar Main Road,
Near Housing Board, Nellithope,
Pondicherry – 605 005
Landmark: Anna Nagar(2nd Floor, Sri Annai Institute)
44.
1PVL-44
Low-Power and Area-Efficient Carry Select ASIC, area-efficient,
Adder
CSLA, low power.
2012
45.
1PVL-45
A Low-Power Single-Phase Clock Multiband frequency synthesizer,
Flexible Divider
high-speed digital
circuits, true singlephase clock
2012
CONTACT : (+91 – 9600 444 787, +91 – 9487 66 2326
MAIL ID : info@1pointer.com, onepointertechnology@gmail.com
WEB SITE : http://www.1pointer.com