DESIGN AND REALIZATION OF THE SECURE CRYPTOGRAPHIC
SHA-3 ALGORITHM FOR EFFICIENT OPERATION
Shivakumar Goud k1, Dr.Savita Sonoli2
1
PG student, Rao Bahadur.Y.Mahabaleswarappa Engineering College Ballari 583104,Karnataka,India.
2
Professor & Head Dept of E&C Rao Bahadur.Y.Mahabaleswarappa Engineering College Ballari 583104,Karnataka,India.
Email:1kshivakumargoud@gmail.com ; 2savitachitriki@gmail.com
Abstract-The protected hash calculation by SHA-3 is
selected and utilized to give security to any application
which assists hashing. This algorithm has been selected
in 2012.The reason for selecting this algorithm depends
on its security, performance and complexity. In this
paper, image data is taken and applied to the SHA-3
algorithm, approach is made to get less error detection
and obtain the original image. The aim is to have
acceptable complexity and performance overheads and
maintaining
high
error
coverage.
Hardware
implementation using FPGA is done and results are
realized in this paper.
Index Terms – Secure hash algorithm (SHA)-3, rotated
operands (RERO).application specific integrated circuit
(ASIC).message digest (MD)5.
1. INTRODUCTION
D u e t o t h e successful attacks happened on the
algorithms MD5, SHA-0, SHA-1 and SHA-2. A secured
hash algorithm known as (SHA)-3 was initiated by the by the
National Institute of Standards and Technology (NIST) in
2007 to increase security and performance of hash functions.
The winner algorithm after three rounds of assessments
chosen in 2012 was keccak. Keccak, the winner of the SHA-3
competition, is expected to provide confidentiality to various
securities. It can be operated as security measure for mobile ad
hoc networks (MANETs) which have problems on physical
layer security. With the help this secure hash algorithm it is
possible to achieve integrity assurance for buildings, smart
fabrics, Internet of Nano-Things, and smart infrastructures as
well as building automation systems, networked control
systems, and wireless sensor networks. Finding faults
occurring in the cryptographic hardware systems, several error
detection approaches have been presented but by using
RERO-based approach, it is possible to achieve low hardware
overhead designs, suitable for lightweight and low- power
implementations.
Natural faults (defects) detection has been the center of
many previous works .Thus, reliability and fault immunity
for the hardware implementations against natural defects
need to be among the assessment aspects for the SHA-3.
2. HASHING ALGORITHM KECCACK
Keccack uses the sponge construction for security purpose
and all generic attacks. It is from the family of hash
function which is based on the sponge function family.
Keccack-f is a permutation composed from the set of
seven keccack-f permutations denoted keccack-f [b]
,where b ∈ {25, 50, 100, 200, 400, 800, 1600} is the
width of the permutation. The width of the sponge
construction is same as the width of the permutation. The
state is organized as an array of 5×5 lanes , each of length w
∈ {1, 2, 4, 8, 16, 32, 64}. For obtain the Keccak [r, c]
sponge function, with parameters capacity c and bitrate r, if
we apply the sponge cons- truction to Keccak- f [r+c ] and by
applying a s pecific padding to the message input. There are
seven possible types for Keccak and for the sake of
brevity, we focus on the recommended type, namely, Keccakf[r + c = 1600] (c = 1024 and r = 576). In Keccakf[1600], 1600 is the width of the underlying permutation (in
bits). For this type of Keccak, the state consists of an array of
5 × 5 lanes, each of length w = 64 bits. The recommended
number of rounds for Keccak-f[1600] is 25.
2.1. A RERO based method
RERO is a method used for error detection introduced
for arithmetic units. As mentioned earlier, it is a
redundancy-based m e t h o d . L e t R and R−1 are nbit rotations towards the least and most significant bits of
a binary operand, where n is less than the size of the
operand .Let x be the input to an arithmetic function f
and f (x) be its output in such a way that R−1 (f (R(x)))
= f (x).To apply the RERO method, t h e result of the f
(x) computation (first run) and compare it against the
result of the R−1 (f (R(x)) computation. If any difference
in results it indicates the presence of error.
The Keccack algorithm consists of five steps. The four
steps (Θ, ρπ, χ, ι) of hash function keccak have data
dependency of first level,ie, the current step depends
only of the outcome of the previous step. This feature
allows exploring techniques of parallelism in
hardware.
(integrated controller) to control trigger ports of ILA in
PC.
Fig 3: Architecture of the whole core.
Fig 1: Five steps in Keccack algorithm.
The permutation module begins its calculations, by
keeping its buffer cleared, and padding module will be
waiting for input simultaneously.
The permutation module is composed of a combinational
logic block computing a round, a register for storing the
output and a counter for selecting the round constant.
3. METHODOLOGY
4. RESULTS
1. Consider an error detection approach based on the timeredundancy techniques, i.e., the recompiling with rotated
operands (RERO) scheme. Through the RERO-based
approach, low hardware overhead is added to the original
designs, suitable for lightweight and low power
consumption.
2. To evaluate the error detection capability of the
proposed scheme in response to transient and permanent
faults, the proposed error detection structures are
simulated. Through our simulations, we demonstrate that
the proposed scheme reaches high error coverage.
3. Finally, the original SHA-3 and our proposed error
detection scheme are synthesized using a 65-nm ASIC
standard-cell library to obtain the area overheads and the
performance metrics.
After simulation done by the Xilinx 13.4v software the
input and output images were compared and in the output
image there is presence of noise.
The given input image is not completely recovered from
the output image.
The output obtained from the FPGA vertex 5 through chip
scope pro displayed in PC is captured and the snapshot of
it is as shown below.
After simulation by Xilinx 13.4v software the output
FPGA Vertex 5 The result is displayed on Chip scope Pro
through ILA (Integrated logic analyzer).
Fig 2: Implementation setup Block diagram.
1. Image is converted into pixels using mat lab code, all
pixels are stored in ROM IP core and for reading from
memory required address and is providing from counter.
2. From memory the pixel data is read and stored in the
buffer and applied to SHA-3.
3. After simulation by Xilinx 13.4v software the output
FPGA Vertex 5 displays output on Chipscope Pro
through ILA (Integrated logic analyzer) and ICON
Fig 3: Input and output comparision by FPGA vertex 5
Table 1: Summary of resource utilization
5. CONCLUSION
Taking image as an input is applied to the SHA-3
algorithm and found the presence of noise in the output
image obtained.
Efforts can be made to recover the input image data
without any error detection in the obtained output image
by using the keccack algorithm.
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