Instrumentation Development Laboratory
SciFi Tracker
DAC driving and mapping
Author: Peter Orel
Checked by: Gary S. Varner
Approved by: Gary S. Varner
Monday, February 8, 2016
Table of Contents
1
Introduction .......................................................................................................................................... 3
2
Daughter-card DAC (DAC128S085) ....................................................................................................... 4
3
2.1
Driving interface............................................................................................................................ 5
2.2
Initialization and serial input register ........................................................................................... 5
2.3
Output mapping ............................................................................................................................ 7
Power-board DAC (LTC2630-HM12) ..................................................................................................... 8
3.1
Driving Interface............................................................................................................................ 9
3.2
Translating to high-voltage ......................................................................................................... 10
2
1 Introduction
In this document we show how the DAC on the daughter cards and power-board are to be operated.
3
2 Daughter-card DAC (DAC128S085)
This is a 12bit SPI DAC from Texas Instruments. It has 8 channels with rail-to-rail outputs. Its datasheet
can be found on:
http://www.ti.com/lit/ds/symlink/dac128s085.pdf
The output can swing from 0V to the Vref which in our case is 5V. The transfer characteristics follows the
following equation:
𝑉𝑂𝑈𝑇 =
𝐶𝑜𝑢𝑛𝑡𝑠 ∙ 𝑉𝑅𝐸𝐹 𝐶𝑜𝑢𝑛𝑡𝑠 ∙ 5
=
[𝑉]
212
4096
5
4.5
4
Voltage [V]
3.5
3
2.5
2
1.5
1
0.5
0
0
500
1000
1500
2000
2500
Counts
3000
3500
4000
4500
Figure 1: DAC Voltage output vs Counts
Where the LSB bit is 1.2mV. To get the output voltage the mentioned equation can be reversed:
𝐶𝑜𝑢𝑛𝑡𝑠 = 𝑟𝑜𝑢𝑛𝑑 (
𝑉𝑂𝑈𝑇 [𝑉] ∙ 212
)
5[𝑉]
Notice the use of the round function. This means that the counts have to be an integer value.
4
2.1 Driving interface
The DAC is driven by a serial 3-wire SPI interface which can be clocked up to 40MHz. A write sequence
begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit
serial input register on the falling edges of SCLK. To avoid mis-clocking data into the shift register, it is
critical that the SYNC line is not brought low on a falling edge of the SCLK. On the 16th falling edge of SCLK,
the last data bit is clocked into the register. The write sequence is concluded by bringing the SYNC line
high. Once SYNC is high, the programmed function (a change in the DAC channel address, mode of
operation and/or register contents) is executed. To avoid mis-clocking data into the shift register, it is
critical that SYNC be brought high between the 16th and 17th falling edges of SCLK [1].
Figure 2: DAC SPI timing diagram
2.2 Initialization and serial input register
The DAC accepts a 16bit word which is divided into two blocks.


Bits 15 to 12 are used to control the mode of operation
Bits 11 to 0 control the output setting of the voltage or a special function setting if used.
The DAC has two modes of operation:


WRM (write register mode) DB[15:12]=1000
This is the default wake-up mode, where writing into the register doesn’t affect the outputs.
WTM (write through mode) DB[15:12]=1001
This mode is where the output gets updated immediately after the writ sequence
5
For setting the output voltage the input register needs to be written. The first 12 bits DB[11:0] of the 16bit
word are used for inputting counts value while. Bits 14 to 12 DB[14:12] are used to select the specific
output (1 to 8). Bit 15 must be a logic 0.
Figure 3: Input register table
The special function will not be required in this application therefore will not be discussed in this
document.
EXAMPLE:
The DAC wakes up at 0V on all outputs (input register filled with 0s) and in the WRM mode. Since we
don’t need all of the outputs to be updated at the same time we can immediately set the mode to WRT
by sending command: 1001000000000000. After we can begin with writing each output individually by:
0001001011100011. In this example we are writing DAC number 1 with a voltage of 0.9V.
6
2.3 Output mapping
In the daughter-card the output map to specific channels. The following table summarizes the channel
mapping:
DAC CS
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
Output Address
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Physical channel
NOT USED
CH11
CH14
CH15
CH13
CH10
CH8
CH7
CH12
CH9
CH6
CH3
CH4
CH1
CH5
CH2
7
3 Power-board DAC (LTC2630-HM12)
This is a 12bit, single channel, SPI driven DAC. Its datasheet can be found on:
http://cds.linear.com/docs/en/datasheet/2630ff.pdf
The output can swing from 0V up to the internal reference, which in our case is 4.096V or alternatively it
can be set to use the power supply as reference in which case the full range is 5V. The transfer
characteristics follows the following equation:
𝑉𝑂𝑈𝑇 =
𝐶𝑜𝑢𝑛𝑡𝑠 ∙ 𝑉𝑅𝐸𝐹 𝐶𝑜𝑢𝑛𝑡𝑠 ∙ 𝑉𝑅𝐸𝐹
=
[𝑉]
212
4096
5
4096mV REF
5000mV REF
4.5
4
Voltage [V]
3.5
3
2.5
2
1.5
1
0.5
0
0
500
1000
1500
2000
2500
Counts
3000
3500
4000
4500
Figure 4: DAC Voltage output vs Counts
Where the LSB bit is 1.2mV for 5V reference and 1mV in the case of the internal reference. To get the
output voltage the mentioned equation can be reversed:
𝐶𝑜𝑢𝑛𝑡𝑠 = 𝑟𝑜𝑢𝑛𝑑 (
𝑉𝑂𝑈𝑇 [𝑉] ∙ 212
)
𝑉𝑅𝐸𝐹 [𝑉]
8
3.1 Driving Interface
The SPI interface can be clocked up to 50MHz. The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, enabling the SDI and SCK buffers and the input shift register. Data (SDI
input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then 4
don’t-care bits; and finally the 16-bit data word. The data word comprises the 12-bit input code, ordered
MSB-to-LSB, followed by 4 don’t-care bits. Data can only be transferred to the device when the CS/LD
signal is low, beginning on the first rising edge of SCK. SCK may be high or low at the falling edge of CS/LD.
The rising edge of CS/LD ends the data transfer and causes the device to execute the command specified
in the 24-bit input sequence.
This DAC wakes up at mid-range (2.048V or 2.5V) which is necessary for our application. The commands
that can be used are shown in the following table:
This command are set by using the bits 24 to 21
Bit sequence DB[24:21]
0000
0001
0011
0100
0110
0111
Command description
Write to input register
Update DAC register and power up
Write, update and power up
Power Down
Select internal reference
Select PS as reference (Vref=Vcc)
The timing diagram of the sequence is shown in the following figure:
Figure 5: DAC timing diagram
At startup the DAC is at mid-supply and the internal reference is used. If we want to set the voltage range
to 5V we can use the command code 0111. During this operation the other 16bits are ignored.
Then to set the output voltage we perform a write sequence:
0011 0000 1011 0011 1001 0000
Where we write and update the output voltage to a value of 2.87V
9
3.2 Translating to high-voltage
The DAC drives a high voltage power supply EMCO SIP90. Where the output voltage follows the given
equation:
𝑉𝑂𝑈𝑇 = 90.5 − 14.1 ∙ 𝑉𝐷𝐴𝐶
100
5000mV REF
4096mV REF
90
High Voltage Out [V]
80
70
60
50
40
30
20
0
0.5
1
1.5
2
2.5
3
DAC vooltage [V]
3.5
4
4.5
5
Figure 6: High voltage out vs DAC voltage
The following equation can be used to simply convert from one voltage/counts to the other:
𝑉𝐷𝐴𝐶 =
90.5 − 𝑉𝐻𝑉 𝐶𝑜𝑢𝑛𝑡𝑠 ∙ 𝑉𝑅𝐸𝐹
=
14.1
212
10