CEC 222 Digital Electronics Lab
Spring 2015
Lab 5: Multi-Input / Multi-Output Logic
Learning Objectives:

Provide additional experience using K-maps to minimize logic expressions.

Reinforce various realizations of minimal logic forms.

Develop familiarity with the ubiquitous 7-segment display.
Lab Overview:
A 7-segment display is a very common low-cost output device for displaying numbers
and alphanumeric characters. The device consists of seven individual LEDs configured in a
“figure 8” pattern. There is also, typically an eighth LED, which is used to represent a period
or decimal place. The seven main LEDs are usually labeled “a”
through “g” and all share a common anode. Thus, the individual
segments can be turned on by enabling individual LEDs and the whole display can be
controlled with the common anode.
A classic application of the 7-segment display is to display hexadecimal (i.e., base 16 = 24) digits which can
be encoded by 4-bits. In this lab you will be developing a four-input to seven-output logic block that accepts a 4bit pattern and drives the 7-segment device(s) on your FPGA board to display the appropriate HEX digit.
SW3
SW2
SW1
SW0
w
x
y
z
4-input
7-output
Logic Block
a
b
…
g
Figure 1 A 4-input / 7-output logic block.
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Lab 05
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CEC 222 Digital Electronics Lab
Spring 2015
Pre-Lab (10%)
Your BASYS 2 board includes four 7-segment displays, each with an independent anode control line. For a
given display, each of the individual seven segments can be illuminated by grounding (i.e., applying a low voltage
=> binary 0) its cathode (i.e., “a” through “g”). Thus, to “turn on” a segment set the corresponding bit to “0.”
Task 1.
Inputs
(wxyz)
Fill in the remaining entries of Table 1.
Table 1 Truth Table of the 7-Segment Display
7 Segment Outputs
HEX
a
b
c
d
e
f
0000
0
0001
1
0010
0
0011
0
0100
1
0101
0
0110
0
0111
0
1000
0
1001
0
1010
0
1011
1
1100
0
1101
1
1110
0
1111
0
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g
0
1
0
0
1
0
1
0
0
0
0
0
Note that patterns for “b” and
“d” are intentionally lower
case, otherwise they would be
indistinguishable from “8” and
“0,” respectively.
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CEC 222 Digital Electronics Lab
Task 2.
Spring 2015
Complete the seven four-variable K-maps corresponding to the seven output columns “a”
through “g” of Table 2.
Task 3.
Develop the minimum SOP or POS expressions requested below (a is given).
Table 2 K-maps for all of the seven segments
a
b
wx
00 01 11 10
yz
00 0 1 0 0
c
wx
00 01 11 10
yz
00
01
1
0
1
0
01
11
0
0
0
1
11
10
0
0
0
0
10
MIN SOP FORM:
a = w’x’y’z + w’xy’z’ + wxy’z + wx’yz
wx
00 01 11 10
yz
00
01
11
1
10
0
MIN SOP FORM:
c=
e
wx
00 01 11 10
yz
00
wx
00 01 11 10
yz
00
01
11
10
f
wx
00 01 11 10
yz
00
01
01
11
0
10
0
MIN SOP FORM:
11
0
10
0
MIN POS FORM:
d=
1
MIN SOP FORM:
b=
d
0
e=
0
1
MIN POS FORM:
f=
g
wx
00 01 11 10
yz
00
01
11
10
0
0
There is ample opportunity for small errors
which may lead to other errors.


MIN SOP FORM:
g=
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
Lab 05
Check your work very carefully!!!
Do not panic if you do not get every
expression perfect!!
In lab you can ask a TA or the
instructor for help!!
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CEC 222 Digital Electronics Lab
Spring 2015
Experiments (90%)
EXPERIMENT 1.
IMPLEMENTING THE HEX TO 7-SEGMANT DISPLAY LOGIC
In this first experiment you will be implementing a fourinput to seven-output logic block (see Figure 1) that accepts a
4-bit pattern, which encodes a HEX number 0 through F, and
drives the 7-segment device(s) on your FPGA board to display
the encoded HEX digit.
Step 1.a: Develop a schematic for each of the seven individual
outputs (a through g).

Copy the file “Lab_5.zip” to an appropriate location and
uncompress the file.

Start ISE and open the project file “Lab_5.xise.”

Click on the “Design” tab in the lower left pane and you
should see a partially completed project (see Figure 2).

Click on the “Options” tab and under “When you click
on a branch” choose “Select the line segment.”

For each of the seven segments, namely, “a” through
“g” you will be developing a symbol with the required
mimimal form of logic (see below for details)
 Some blocks already exist, however, the
contents (or partial contents) may NOT be
Figure 2 Partially completed project
correct!!!
 To edit/view the contents of an existing symbol right click on the symbol
and select Symbol -> Push into symbol. You can now edit the contents
of the existing symbol.
 For missing segments you will need to create a new symbol.

Use the select Tools -> Symbol Wizard to create a symbol
entitled “segment_?”

At the bottom of the schematic (my_7_seg.sch), the four LEDs are connected to
the four inputs w (=LED3), x (=LED2), y (=LED1), and z (=LED0).
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CEC 222 Digital Electronics Lab

Spring 2015
Develop an AND / OR schematic implementation of the min SOP logic for output “a”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “a”

Develop an AND / OR schematic implementation of the min SOP logic for output “b”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “b”

Develop an NAND / NAND schematic implementation of the min SOP logic for output “c”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “c”

Develop an AND / OR schematic implementation of the min SOP logic for output “d”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “d”

Develop an OR / AND schematic implementation of the min POS logic for output “e”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “e”

Develop an NOR / NOR schematic implementation of the min POS logic for output “f”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “f”

Develop an NAND / NAND schematic implementation of the min SOP logic for output “g”
 The input ports should be named “w”, “x”, “y”, and “z” and output port named “g”
Step 1.b: Complete the main schematic named “my_7_seg.”

In the main schematic named “my_7_seg” insert the necessary symbols to ensure that you have
included ALL of the seven symbols that you have just created or modified (i.e., segment_a to
segment_g).

The four inputs, common to all seven symbols, should be connected to ports named “w”, “x”, “y”, and
“z.”

The seven outputs should be connected to ports named “a,” “b,” … “g.”

Note that the *.ucf file has already been added to your project. Your input and output signals MUST
match the names in this file!!!
Step 1.c: Program the FPGA.

In ISE synthesize, implement, and generate the programming file.

Load the “my_7_seg.bit” file into your FPGA.
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CEC 222 Digital Electronics Lab
Spring 2015
Report Requirements
Task 4.
Use the switches, SW3 to SW0, to select each of the 16 input combinations. For each input
combination insert a photo of the switches and 7- segment display in empty cells of Table 3 (two
examples are provided).
Table 3 Photos of 7-Segment Display and Switch Inputs
0
8
1
9
2
A
3
b
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CEC 222 Digital Electronics Lab
Spring 2015
4
C
5
d
6
E
7
F
Optional Exercise(s) (+10% Extra Credit)
EXPERIMENT 2.
SIMPLIFYING THE LOGIC FURTHER
Adjacent diagonal entries in the K-map correspond to XOR type relationships. Revisit the schematic for
segment “a” (see output “a” in Table 2) and develop a simple alternative logic expression, including two 2-input
XOR gates.
a = _______________
Task 5.
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Capture a screenshot of your updated schematic in Figure 3 below.
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CEC 222 Digital Electronics Lab
Spring 2015
Figure 3 Updated schematic for “segment_a.”
Reference Material
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