WP10 LPSC 09/10/15 18A 1/18 Pierre Auger Observatory Surface Detector Electronics Upgrade UUB Pre Prototype H/W Modifications UUB Model version: SDE-002-002-IE00 Document written by: E. Lagorio Institute: LPSC Grenoble Date: 09 Octobre 2015 ATRIUM Reference: TBD Document1 verified by: P. Stassi Date: Project Reference: 09 Octobre 2015 WP05-LPSC-18A 07/02/16 22:02 - 1 / 18 WP10 LPSC 09/10/15 18A 2/18 Table of Content 1. Power supplies: ..................................................................................................................................................... 5 1.1. Valid_Alim modification: ............................................................................................................................ 5 1.2. DC/DC starter: ............................................................................................................................................. 5 1.3. Power supplies enable without Slow-Control Firmware: ............................................................................ 6 1.4. To enable 5V, 3V3, 1V2/1V8 and P3V3ANA/N3V3ANA power supplies: ............................................... 6 1.5. Optimization: ............................................................................................................................................... 7 1.6. Fake MAX4080SASA component: ............................................................................................................. 7 1.7. 10 V DC/DC current limit: .......................................................................................................................... 8 2. RESET & DONE configuration: ........................................................................................................................... 9 3. Zynq: ................................................................................................................................................................... 11 4. LED-CONTROLER: .......................................................................................................................................... 12 1.8. I²C interface: .............................................................................................................................................. 12 1.9. LED Controller power supply selection: ................................................................................................... 12 1.10. 24 Volts & 12 Volts decoupling tantalum capacitor: ................................................................................. 13 5. Cleaner Jitter: ...................................................................................................................................................... 15 6. 120 MHz Oscillator control DAC: ...................................................................................................................... 16 7. Front-end: ............................................................................................................................................................ 17 1.11. SDIO bidirectional interface: ..................................................................................................................... 17 1.12. ADCs hardware configuration: .................................................................................................................. 17 1.13. VREF Voltage reference: .......................................................................................................................... 18 Document1 07/02/16 22:02 - 2 / 18 WP10 LPSC 09/10/15 18A 3/18 ACRONYMS ADC BGA CR DC ER FPGA FR GPS ICD IR n/a OR PBS PCB PR QR SDE SR TBC TBD TBW UB UUB UHE UHECR VM Analog to Digital Converter Ball Grid Array Configurational Requirement Direct Current Environmental Requirement Full Programmable Gate Array Functional Requirements Global Positioning System Interfaces Control Document Interface Requirements non applicable Operational Requirements Product Breakdown Structure printed Circuit Board Physical Requirements Quality Requirements Surface Detector Electronics Support Requirements To Be Confirmed To Be Defined To Be Written Unified Board Upgraded Unified Board Ultra High Energy Ultra High Energy Cosmic Ray Verification Matrix Document1 07/02/16 22:02 - 3 / 18 WP10 LPSC 09/10/15 18A 4/18 DOCUMENT CHANGE RECORD Issue Revision 18 A Document1 Issue Date 09/10/15 Changes Modified Pages Numbers, Change Approved by Explanations and Status E. Lagorio First version 07/02/16 22:02 - 4 / 18 WP10 LPSC 09/10/15 18A 5/18 1. POWER SUPPLIES: 1.1. Valid_Alim modification: The Valid_Alim is generated by 1 Volt DC/DC converter, from its “power good” pin. R100_1 is removed. A 1,5 K Ohms is added between VDD (U86_1 pin 10) and PGOOD (U86_1 pin 11). Figure 2:Valid_Alim modification on UUB Figure 1: Valid_Alim modification in schematic (page 11) 1.2. DC/DC starter: 10 nF capacitors C58_1, C101_1, C104_1 and C267_1 was changed by 100nf capacitors (schematic pages 9 & 10). C101_1 C58_1 C267_1 C104_1 Figure 3: Power Supply Enable resistors on UUB(Schematic page 9, 10 & 11) Document1 07/02/16 22:02 - 5 / 18 WP10 LPSC 09/10/15 18A 6/18 1.3. Power supplies enable without Slow-Control Firmware: To enable 1 Volt DC/DC converter, without Slow-Control Firmware, Q6_1 transistor pin 2 and 3 must be connected. In the next board a 0 Ohm resistor will be added in the schematic. Figure 4: 1 Volt Power Supply Enable (Schematic page 11) Figure 5: 1 Volt Enable modification on UUB *The wire will be shorter. 1.4. To enable 5V, 3V3, 1V2/1V8 and P3V3ANA/N3V3ANA power supplies: R171, R183, R187 and R193 must be soldered (Schematic page 10 & 11). R171 (bottom) R187 R193 R183 Figure 6: Power Supply Enable resistors (Schematic page 10 & 11) Those resistors must be removed if Slow-Control Firmware is used. Document1 07/02/16 22:02 - 6 / 18 WP10 LPSC 09/10/15 18A 7/18 1.5. Optimization: 22 kOhms resistor R133_1 is removed (Schematic page 10). R133_1 removed Figure 7: R133_1 resistor removed on board Figure 8: R133_1 resistor removed (Schematic page 10) 1.6. Fake MAX4080SASA component: MAX4080SASA (60V/V gain) components on the board work like MAX4080TASA (20V/V gain) components. There are 12 on each boards. They have been changed by new component with same reference from Farnell. Design reference: U73_1, U74_1, U75_1, U79_1, U80_1, U81_1, U82_1, U88_1, U89_1, U90_1, U95_1 & U96_1. Figure 9: new MAX4080SAS components (Schematic page 9, 10 and 11) MAX4080SASA Figure 10: new MAX4080SAS components on the UUB Document1 07/02/16 22:02 - 7 / 18 WP10 LPSC 09/10/15 18A 8/18 1.7. 10 V DC/DC current limit: R73_1 resistor value changes to 330 Ohms. This resistor limits the output current from 10 Volts DC/DC. Figure 11: Current limit R73_ resistor for 10 Volts DC/DC (Schematic page 9) R73_1 Figure 12: Current limit R73_ resistor for 10 Volts DC/DC on the UUB Document1 07/02/16 22:02 - 8 / 18 WP10 LPSC 09/10/15 18A 9/18 2. RESET & DONE CONFIGURATION: There is no Slow-control Firmware in the board. The Reset can be managed by the Slow-Control. R286 & R287 must be removed and R288 & R289 added (Schematic page 12 & 23). This is the reverse operation if there is a Slow-Control Firmware. 4,7 kOhms Pull-up added between 3V3_SLOW_CTRL and U20 pin 23 (schematic page 12). Figure 13: Slow-Control RESET configuration resistors (Schematic page 12) DONE pull-up resistor added R287 removed R286 removed Figure 14: Slow-Control RESET & DONE configuration resistors on board Document1 07/02/16 22:02 - 9 / 18 WP10 LPSC 09/10/15 18A 10/18 Figure 15: RESET Storage flash memories configuration R289 resistor (Schematic page 23) R289 removed Figure 16: RESET Storage flash memories configuration R291 resistor on board Document1 07/02/16 22:02 - 10 / 18 WP10 LPSC 09/10/15 18A 11/18 3. ZYNQ: R296_7 resistor must be changed by a 1 k Ohms and R288_7 must be removed (schematic page 23). *l ; Figure 17: R296_7 resistor changes value and R288_7 removed (Schematic page 23) R288_7 removed R296_7 change value to 1 k Ohms Figure 18: R296_7 resistor changes value and R288_7 removed on board Note: Open Jumper: JTAG configuration. Close jumper: External memory configuration. Document1 07/02/16 22:02 - 11 / 18 WP10 LPSC 09/10/15 18A 12/18 4. LED-CONTROLER: 1.8. I²C interface: Error in the schematic, SCL & SDA pins must be swapped. Figure 19: SCL & SDA wires must be swapped (Schematic page 7) SCL & SDA swap Figure 20: SCL & SDA wires must be swapped on board 1.9. LED Controller power supply selection: R39 must be removed for 5 Volts power supply (schematic page 7). Figure 21: LED-Ctrl power supply resistor selection (Schematic page 7) Document1 07/02/16 22:02 - 12 / 18 WP10 LPSC 09/10/15 18A 13/18 R39 removed Figure 22: R39 removed for 5 Volts power supply on UUB 1.10. 24 Volts & 12 Volts decoupling tantalum capacitor: C21 & C23 value must changes because the capacitor’s voltage for 150µF is 10Volts. Those capacitors are used for 24 Volts (up to 33 Volts) and 12 volts. The value is changed by 10 µF and 35 Volts tolerance. Figure 23: C21 &C23 value changes for 10µF and 35 Volts (Schematic page 7) Document1 07/02/16 22:02 - 13 / 18 WP10 LPSC 09/10/15 R21 changed 18A 14/18 R23 changed Figure 24: C21 &C23 value changes for 10µF and 35 Volts on UUB Document1 07/02/16 22:02 - 14 / 18 WP10 LPSC 09/10/15 18A 15/18 5. CLEANER JITTER: 0 Ohm resistor R296, R298 & R314 must be removed (schematic page 6). Figure 25: Cleaner Jitter configuration resistors (Schematic page 6) R295 removed R314 removed R296 removed Figure 26: Cleaner Jitter configuration resistors on board Document1 07/02/16 22:02 - 15 / 18 WP10 LPSC 09/10/15 18A 16/18 6. 120 MHZ OSCILLATOR CONTROL DAC: DAC7551 IOVDD pin must be connected to 3,3 Volt (1,8 volt previously) power supply and the pull-up resistors R382, R383, R384, R385 & R386 too. Figure 27: DAC7551 Power supply modifications (Schematic page 6) 3.3 Volts power supply modification Figure 28: DAC7551 Power supply modifications on uub Document1 07/02/16 22:02 - 16 / 18 WP10 LPSC 09/10/15 18A 17/18 7. FRONT-END: 1.11. SDIO bidirectional interface: R97 value changes from 10K Ohms to 1K Ohms (Schematic pages 24). Figure 29: R97 resistors 1K Ohms value (Schematic page 6) R97 changed value to 1 K Ohms Figure 30: R97 resistor value changes to 1 K Ohms on board 1.12. ADCs hardware configuration: All /CS pull-up R40_1, R40_2, R40_3, R40_4 & R40_5 resistors must be removed (Schematic 16, 17, & 18 pages). All SDIO pull-up R34_1, R34_2, R34_3, R34_4 & R34_5 resistors must be removed (Schematic 16, 17, & 18 pages). SCK pull-up R32_1, R32_2, R32_4 & R24_5 resistors must be removed (Schematic 16, 17, & 18 pages) Figure 31: SDIO pull-up removed (Schematic page 18) Document1 Figure 32: SDIO pull-up removed (Schematic pages 16, 17, 19 & 20) 07/02/16 22:02 - 17 / 18 WP10 LPSC 09/10/15 18A 18/18 /CS, SCK & SDIO pullup resistor removed (pages 16, 17, 19 & 20) /CS & SDIO pull-up resistor removed (pages 18) Figure 33: SDIO pull-up removed on UUB 1.13. VREF Voltage reference: R336 and R339 values must be swapped: Figure 34: VREF resistor values must be swapped (Schematic page 15) R339 value changes to 1 K Ohms R336 value changes to 330 Ohms Figure 35: VREF resistor values must be swapped on UUB Document1 07/02/16 22:02 - 18 / 18