Ankitha Miryala 310_Lab6
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Ankitha Miryala Section 7 PSU ID: 950603219 TA: Alexander Cocking Formal Design Report EE 310 Electronic Circuit Design Fall 2013 Experiment 6 Project: Amplifier Design Using an Active Load Introduction: In this experiment we will design an amplifier circuit, which will provide a gain. We will be using the CD4007 chip that we used in the experiment 4 and 5. Amplifiers are an important part of analog circuits. MOSFETs can be configured in such a way that a small ac input signal gives a significantly larger ac output signal. One common way of doing this is to use PMOS transistors to construct a current mirror to act as an active load for an amplifying NMOS transistor. The main purpose of this experiment is to observe the voltage gains of the various amplifier configurations and also observe how the body effect changes the voltage gain. Basically we will be constructing an AC amplifier using CMOS devices and using a current source as an active load. First a basic common-emitter circuit is constructed and examined and the measured voltage transfer characteristic is compared to the expected results. Then the common-gate configuration is examined and compared to the expected values. Here we also take into account the body effect and finally the body effect current is characterized using a specially designed circuit. Table listing of the parameters for the MOSFETs from Lab 4: Device K(πA/V2) π (per mV) VA (volt) NMOS1 150 7.6 131.58 NMOS2 420 7.8 128.21 NMOS3 420 6.8 147.06 PMOS1 336 0.0420 23809.52 PMOS2 331 0.0419 24449.88 PMOS3 334 0.0421 23752.97 CIRCUIT SCHEMATICS Task1 - Current Mirror/Active Load Schematic Figure 1 - Current Mirror/Active Load The 50 k resistor in series with the ammeter insures that VSD2 in this test is +5V; the same value as it will be in the actual amplifier circuit (Figures 3 and 4). Task 2 – Common-Source Amplifier Circuit Schematic Task 5 – Common-Gate Amplifier Circuit Schematic Figure 5: Schematic of ac equivalent circuit of the circuit shown in Figure 2, if the source Vi is moved to node Y and node X is grounded. Task 7 – Directly Measuring the Body Effect Schematic Figure 7: Schematic of circuit in Figure 2 if vi is connected to node Z and nodes X and Y are both grounded. DATA AND GRAPHS Task 1 Theoretical calculation of VGS2, R3 ππ· = πΎπ (πππΊ − πππ ) πππΊ = √ππ· ⁄πΎπ − πππ ππ πΈπΉ = 100ππ΄ = ππ· πππΊ = √100ππ΄⁄0.331ππ΄ – 1.53π πππΊ = 2.08π : Theoretical value By KVL, π 3 = ππ·π· − πππ − πππΊ ππ πΈπΉ π 3 = 10 − 0 − 2.08 100ππ΄ π 3 = 79.2πΎΩ : Theoretical value Measured Value of π 3 π 3 = 90.8πΎΩ Task 2 Theoretical calculation of VGS1, R1, R2 Here we have to calculate ππΊπ1 to make Io = 100ππ΄ Assume π π πΌπ· = πππ· βͺ 1 ππΊπ = ( π 2 ) 10π π 1 + π 2 And ππΊπ = √ππ· ⁄πΎπ + πππ ππΊπ = √100ππ΄⁄0.42π + 1.14π ππΊπ =1.628V π 1 = ππ·π· − πππ − ππΊπ 10ππ΄ π 1 = 10 − 0 − 1.628 10ππ΄ π 1 = 837.2πΎΩ π 2 = ππΊπ 10ππ΄ π 2 = 1.628π 10ππ΄ π 2 = 162.8πΎΩ Check: ππΊπ = ( 162.8πΎΩ ) 10π 837.2πΎΩ + 162.8πΎΩ ππΊπ = 1.628π Hence true. Task 3: Record method used to adjust R1/R2 Here we are adjusting the Q-point of the device To do this we use potentiometers to adjust the resistances to get the desired value of current and output voltage R1/R2 was adjusted using π 2 = 250πΎΩ potentiometer connected in series with R1 and adjusted until the DC Q point was at approximately 5V (i.e. halfway between the supply voltage and ground) We choose π 2 = 250πΎΩ pot to adjust the voltage π 3 = 100πΎΩ pot to adjust the current We have to adjust pots so that πππ·πΆ = 5π and πΌπ = 100ππ΄ Here, we altered R2 so that the output voltage ππ_π·πΆ = 5π Record actual R1, R2, Vo From DMM we measured the respective values as below: π 1 = 848πΎΩ (we used a 820πΎΩ and a 18πΎΩ in series) π 2 = 178πΎΩ (we altered R2 so that the output voltage) ππ_π·πΆ = 5π Measure VGS1, VGS2, ID1 ππΊπ1 = 1.52π of NMOS πππΊ2 = −1.96π of PMOS πΌπ = πΌπ·1 = 103ππ΄ schematic) = 184kohm Multimeter XMM1 = Vo = 5.204 V XMM2 = -V_GS2 = 1.952V XMM3 *A/V = 97.467 uA XMM4 = V_GS1 = 1.677V The oscilloscope CH1 = Vo CH2 = Vi Av = Vo/Vi = 76 v/v Error%(V_GS1) = (1.677-1.45)/ 1.677 = 13.5% Error%(V_GS2) = (2.02- 1.952)/1.952 = 3.5% Error%(Id) = (97.46-93)/97.46 =4.6% The main differences between simulated results and the actual value of the lab should result from the different parameters used by the MULTISM and those of my own chips. In addition, the multimeter can also interfere with the results. Task 4 Small signal equivalent circuit & calculation of Av, Rin, Rout As we are done with the circuit biasing we will now add an AC signal at node X in the figure for an AC amplifier. This is respectively done in the small-signal model as well ππ1 = 1 1 = = 1.316ππΊ ππΌπ·π 0.0076 ∗ 100π − 6 ππ2 1 1 = = = 238.1ππΊ ππΌπ·π 0.0420 ∗ 100π − 6 ππ·π = 5.2π from DMM ππ = 2√πΎπ ∗ πΌπ·π (1 + πππ·π ) = 2√ 150ππ΄ π£2 ∗ 100ππ΄(1 + 0.0076 ∗ 5.2) = 249.74πS π£π = −ππ ∗ π£ππ (ππ1 ||ππ2 ) π£π = π£ππ π£π = −ππ ∗ (ππ1 ||ππ2 ) π£π π£π π£π =249.74πS∗ (201.6ππΊ) = −50.35π/π is AV(THEORITICAL) To find the values of RIN and ROUT, one must reduce to the circuit by removing any sources and adjusting components as shown above. Each resistor can then be calculated by obtaining the correct equivalent equations. To find the values of Rin and Rout we should remove all the sources to get the equivalent resistances at both the ends. π ππ’π‘ = ππ1 ||ππ2 = 201.6ππΊ π ππ = π 1 ||π 2 = 837.2ππΊ||162.8ππΊ = 136.3ππΊ Plot of Vi and Vo & measurement of Av The plot reveals values for VO and Vi which using the equation AV = VO / Vi allows to determine the voltage gain. One thing to keep in mind is both VO and Vi are positive number on the plot but because they are out of phase the voltage gain is automatically negative. π΄π£ = −508ππ 80ππ = −6.35 is AV(EXPERIMENTAL) We tried hard during the lab but the oscilloscope results did not give a gain close to 140 as it was supposed to be. The discrepancy in the gain is because of our π values of our PMOS from lab 4. Task 5 Small signal equivalent circuit & calculation of Av, Rin, Rout In task 5, we shorted X to ground and sent Vi from Y, making a CG amplifier. We follow the same procedure of Task 4 except in Task 5 the circuit is not a common source amplifier but a common gate amplifier. This makes the AC small signal analysis different by having the gate go to ground instead of source. Also, we will have to take the body effect into consideration. π ππ’π‘ = ππ1 ||ππ2 = 201.6ππΊ π ππ = 51πΊ π΄π£ = (ππ + πππ + 1 )π ππ1 ππ’π‘ π΄π£ = (249.74ππ + 62.44ππ + 0. .02)201.6ππΊ π΄π£ = −629.355π/π this is the π΄π£_πΆπΊ −1.36π π΄π£ = 12.8ππ =-106.26 Task 6 Calculate πππ and πΌ from your measurements ππ = 2 ∗ √πΎπ (1 + ππΌπ·π ) ππ = 249.74ππ πππ = η ∗ ππ Taking η = 0.25 as given in the lab instructions πππ = 62.44ππ |π΄π£_πΆπ | ππ ∗ π ππ’π‘ π = = |π΄π£_πΆπΊ | (ππ + πππ ) ∗ π ππ’π‘ π + η 50.35 106.26 η= = π π+η 1 − 1 = 1.11 0.47388 πππ = η ∗ ππ πππ = 249.74ππ ∗ 1.11 = 277.27ππ Task 7 Small signal analysis of test circuit We conclude the experiment by designing a test circuit that measures the body trans conductance and body effect parameter directly. We connect to Vi to node 2 (i.e.) connect node X to node Y, so that we can get gmb directly. Now we get rid of ππ π£ππ current so that we can fing the gmb. AV(MEASURED) = π£π π£π = 1.06π 25.6ππ΄ =41.41V/V π£π = πππ ∗ (ππ1 ||ππ2 ) π£π πππ = (π£_π⁄π£_π) / (ππ1 ||ππ2 )= 2.05*10-4 η= πππ ππ = 2.05∗10−4 249.74∗10−6 = 0.822 AV (TEST) = ≅ π΄π πΆπΊ − |π΄π πΆπ | = 99.156 − |−46.23| = 52.926 DISCUSSION Reasoning behind task 7 test circuit (How does it work?) The circuit used in TASK 7 is similar to the other circuits used in this lab and works very similarly except that the gate and the source are tied together here. Here, we connect node X to node Y and measure the gain from the oscilloscope. From the small signal viewpoint we eliminate the gmvgs so that we gave only this π΄π£ = (πππ + 1 ππ1 )π ππ’π‘ , remaining so that we can directly calculate πππ . Compare theoretical values to measurements Percent Error = |πΈπ₯ππππππππ‘ππ−ππππ π’πππ | πΈπ₯ππππππππ‘ππ ∗ 100% Task 1 – R3 Measured = 90.8πΎΩ Experimental = 79.2πΎΩ Percent Error = 14.7% Task 3 – R1 Measured = 848kβ¦ (Measured from Task 2) Experimental = 837.2kβ¦ Percent Error = 1.29 % Task 3 – R2 Measured = 178 kβ¦ Experimental = 168.23 kβ¦ Percent Error = 5.83 % Task 3 - VGS Measured = 1.52 V Experimental = 1.628 V Percent Error = 6.63 % Task 4 - AV Measured = -50.35 V/V Experimental = -6.35 V/V Percent Error = 6.93% Task 5 – AV Measured = 629.355 V/V Experimental = 106.26 V/V Percent Error = 492.3% Task 6 Vs Task 7 – gmb Measured = 2.77 * 10 -4 S Experimental 2.05× 10−4 S Percent Error = 35.1% Task 6 Vs Task 7 – η Measured = 1.11 Experimental = 0.822 Percent Error = 35.04% Amount of errors and reasons for errors We see that the percentage errors for the resistances show good results and the values are satisfactory. But the huge discrepancy in the gain errors for both common gate and common source is because our π values from lab 4 were off by a factor of 10 and therefore the inaccuracy. We tried very hard during the lab and outside of class period but the oscilloscope dint give us the appropriate gain for the common source. We thoroughly understood the lab because of the many errors and obstacles during the lab but our values were off because of the chip parameter errors. We see that theoretical values did not match with the experimental values but we were happy to get satisfactory πππ and π values. Compare measurements to simulated values VO Simulated = 1.176 V Experimental = 1.21 V Percent Error = 3.3% Vi Simulated = 25.44 mV Experimental = 27.8mV Percent Error = 8.63% AV Simulated= 50.26 V/V Experimental = 71.72 V/V Percent Error = 28.2% Amount of errors and reasons for errors From above we can see that most of the values were within the desired range. Errors may be due to the non-ideal experimental conditions such as voltage supplied, DMM resolution and human errors such as calculation approximations etc. Answer questions related to different configurations Why is the voltage gain for the common gate larger than the voltage gain for the common source? Answer: It Is due to how the circuits are for their AC small equivalent circuits. Depending on the set up of the dependent voltage source and location of the resistors we see that the voltage gain for common gate would be larger than the voltage gain for common source. How does the calculated voltage gain compare with the experimental value determined for the amplifier? Can you appreciate the problem of loading effect when measuring either a DC or AC voltage signal at the output node? Answer: The calculated voltage gain is almost similar to the one we got in experimental calculations. We could see the problems of loading effect for both DC and AV voltage signal at the output node, as the sensitivity was very high. How do the experimental values of gmb and η obtained by this test circuit compare with those previously determined? Is there a reason why one of these experimental approaches should be preferable from the standpoints of measurement accuracy and simplicity? Answer: We had 35.1% error in the experimental and theoretical values for body effect parameter and body trans conductance. This may be due to the errors noted above. We could use the theoretical values from the standpoint of accuracy and simplicity as there is less room for errors such as human errors but the experimental value is the one that will be in real conditions and the theoretical value is more for ideal conditions. Summary, Conclusions & Attachments In this experiment we investigated the use of NMOS amplifying transistor with complementary NMOS device configured as a current mirror/active load. We found that the body effect influences the overall small signal gain performance. This came particularly came into play for common gate (CG) and common drain (CD) amplifier configurations. We saw that the body effect increases the amplifier’s voltage gain. We compared various results with the corresponding simulated or theoretical value and we found that the errors was within the acceptable margin. However, some results had a considerable error and this may be due the reasons noted above. The lab report pages are attached to this report, design proposals were submitted in pre-labs at the starting of each lab.
