S3 INFOTECH
+919884848198
VLSI (IEEE 2014) TITLES FOR
BE, B.TECH
S.N
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Project Title
Area–Delay–Power Efficient Carry-Select Adder
Shift Register Design Using Two Bit Flip-Flop
Input Vector Monitoring Concurrent BIST Architecture Using SRAM
Cells
Design and Analysis of Approximate Compressors for Multiplication
High Speed Vedic Multiplier Designs-A Review
Efficient Integer DCT Architectures for HEVC
SDR - Implementation Of Low Frequency Trans-Receiver On FPGA
Design of Dedicated Reversible Quantum Circuitry for Square
Computation
ASIC Design of Reversible Multiplier Circuit
High throughput pipelined 2D Discrete cosine transform for video
compression
Multiplication Acceleration Through Quarter Precision Wallace Tree
Multiplier
Power Evaluation of Sobel Filter on Xilinx Platform
FPGA Based Implementation & Power Analysis of Parameterized
Walsh Sequences
A 1-GHz Direct Digital Frequency Synthesizer in an FPGA
Realization of 2:4 reversible decoder and its applications
On The Systematic Creation of Faithfully Rounded Truncated
Multipliers and Arrays
Low-Complexity Low-Latency Architecture for Matching of Data
EncodedWith Hard Systematic Error-Correcting Codes
Radix-2r Arithmetic for Multiplication by a Constant
Low power Square and Cube Architectures Using Vedic Sutras
A Novel Parallel Multiplier for 2’s Complement Numbers Using
Booth’s Recoding Algorithm
4-2 Compressor Design with New XOR-XNOR Module
A New Design of Low Power High Speed Hybrid CMOS Full Adder
Year
IEEE 2014
IEEE 2014
Tool
Quartus
Quartus
IEEE 2014
IEEE 2014
IEEE 2014
IEEE 2014
IEEE 2014
Quartus
Quartus/Xilinx
Quartus/Xilinx
Quartus/Xilinx
Simulink-XSG
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
Quartus
IEEE 2014
IEEE 2014
Quartus/Xilinx
Simulink-XSG
IEEE 2014
IEEE 2014
IEEE 2014
Simulink-XSG
Simulink-XSG
Tanner
IEEE 2014
Quartus/Xilinx
IEEE 2014
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
IEEE 2014
IEEE 2014
Quartus/Xilinx
Tanner
Tanner
# 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198.
www.s3computers.com
E-Mail: info@s3computers.com
S3 INFOTECH
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
+919884848198
Improved design of high-frequency sequential decimal multipliers
A Decimal / Binary Multi-operand Adder using a Fast Binary to
Decimal Converter
FPGA based Partial Reconfigurable FIR Filter Design
Improved matrix multiplier design for high-speed digital signal
processing applications
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR
Interpolation Filter for Multistandard DUC
Power- and Area-Efficient Approximate WallaceTree Multiplier for
Error-Resilient Systems
HDL Based Implementation of NxN Bit-Serial Multiplier
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With
Low Adaptation-Delay
Single-Bit Pseudo parallel Processing Low-Oversampling Delta–Sigma
Modulator Suitable for SDR Wireless Transmitters
Software/Hardware Parallel Long-Period Random Number Generation
Framework Based on the WELL Method
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
Gate Mapping Automation for Asynchronous NULL Convention Logic
Circuits
Mapping Loop Structures onto Parametrized Hardware Pipelines
Multifunction Residue Architectures for Cryptography
Logical Computation on Stochastic Bit Streams with Linear Finite-State
Machines
Recursive Approach to the Design of a Parallel Self-Timed Adder
Two Phase Clocking Subthreshold Adiabatic Logic
2-Bit Magnitude Comparator using GDI Technique
Implementation Of Barrel Shifter using Diode free Adiabatic Logic
(DFAL)
Implementation of Optimized High Performance 4x4 Multiplier using
Ancient Vedic Sutra in 45 nm Technology
Comparative Analysis of Carry Select Adder using 8T and lOT Full
Adder Cells
Design of Low Power Split Path Data Driven Dynamic Ripple Carry
Adders
Improved 8-Point Approximate DCT for Image and Video Compression
Requiring Only 14 Additions
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet
Filter Banks With Low Adder-Count
Efficient VLSI Implementation of Neural Networks With Hyperbolic
Tangent Activation Function
IEEE 2014
Quartus/Xilinx
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
Quartus/Xilinx
IEEE 2014
IEEE 2014
IEEE 2014
IEEE 2014
Quartus/Xilinx
Quartus/Xilinx
Tanner
Tanner
IEEE 2014
Tanner
IEEE 2014
Tanner
IEEE 2014
Tanner
IEEE 2014
Tanner
IEEE 2014
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
IEEE 2014
Quartus/Xilinx
# 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198.
www.s3computers.com
E-Mail: info@s3computers.com
S3 INFOTECH
48
49
+919884848198
Design and Simulation of Software Defined Radio Using MATLAB
SIMULINK
FPGA Implementation of Stream Cipher Using Toeplitz Hash Function
IEEE 2014
IEEE 2014
Simulink-XSG
Simulink-XSG
Implementation of Error Correcting methods for asynchronous
communication and Modified Completion Detector with reduced area
overhead
IEEE 2014
SimulinkXSG
50
# 10/1, Jones Road, Saidapet, Chennai – 15. Ph: 044-3201 7467, 9884848198.
www.s3computers.com
E-Mail: info@s3computers.com