VCC
Step 1: Triangle wave generator
Figure 1 shows the circuit for a triangle wave generator using an LM339
voltage comparator. The theory of operation can be better understood
by examining Figure 2. The output of the LM339 is an open collector
which presents an open circuit when the voltage at the non-inverting
input is greater that the voltage at the inverting input, and a low
impedance path to ground otherwise; as indicated by the switch in
Figure 2 . Both inputs present a very high (> 107 ohms) impedance.
The voltages presented to the two inputs must be determined for the
two cases of the switch being open and closed. When the switch is
closed, any voltage on C1will discharge through R4 at a
rate corresponding to 1 = R4C1. The voltage applied to
the non-inverting input will be determined by the
voltage divider comprised of R1, R2, and R6. The switch
will remain closed so long as the capacitor voltage
(which is applied to the inverting input of the LM339)
remains higher than the voltage applied to the noninverting input. The instant that the capacitor drops
below the voltage at the common node of R1, R2, and R6
the switch will open.
R5
R1
U5-0
+
R6
V+
V-
-
LM339
R2
R4
C1
Figure 1 Triangle wave generator
Now the voltage at the common node of R4 , R5, and R6 is no longer zero, but Figure 2 Simplified Schematic
rises instantly to a new value, dependent upon the resistor values. This has
two effects: (1) C1 will begin to charge up towards a value Vth at a rate corresponding to 2 = RthC1 ,
where Rth and Vth represent the thevenin equivalent of the resistor network seen by the capacitor, and
(2) the voltage at the common node of R1, R2, and R6 , applied to the non-inverting input of the LM339
will instantly rise to a new value determined by the resistor network (and to a small extent, by the
changing capacitor voltage). Once these two changes occur, the voltage at the non-inverting input is
substantially higher than the capacitor voltage applied to the inverting input, and the switch will remain
open.
After an interval ~ 2 , C1 will charge up past the voltage at the non-inverting input, and the switch will
close, repeating the cycle. As C1 charges and discharges, its voltage approximates a triangle wave which
will be used in the pulse width modulator. Our job is to choose component values to meet the following
design criteria:
1. The duty cycle of the switch should be 50% +/- 10%
2. The capacitor voltages at the switching points should be 25% and 75% of VCC, +/- 5%. This
implies that the threshold voltages applied to the non-inverting input should also be 25% and
75% of VCC, +/- 5%. respectively
3. One full cycle should take 100 uS +/- 20%
4. The total current through the switch must be less than 10 mA (you may assume VCC = 15 V, but
you are better off leaving it symbolic).
Procedure:
You will need to translate the design criteria into equations which involve the component
values/symbols. There are six unknown component values. If the number of independent equations is
greater than six, then the problem is unsolvable with the given circuit topology. If the number of
equations is less than six, then you will be able to create additional equations like R5 = 4700 (i.e.
choose a value) until you have the same number of equations as unknowns. Solve the set of equations
for the component values. Then choose values close to your computed values from available standard
values, and analyze the resulting circuit to determine whether the design criteria are met to within their
tolerances using your chosen values. This will require the circuit in figure 2 to be analyzed from several
different respects in order to translate the design requirements into solvable circuit equations.
I.
Switch closed
1.
Perform an analysis of the circuit and determine an expression for the voltage at the common
node of R1, R2, and R6 (the threshold voltage applied to the non-inverting input) in terms of VCC
and R1, R2, and R6. Set this expression equal to 0.25 VCC .
2. Perform an analysis of the circuit and determine an expression for the current flowing through
the switch in terms of VCC and the circuit elements. Set this expression equal to 10 mA . For the
worst case, assume that the switch just closed and the capacitor voltage is equal to 0.75 VCC.
3. Perform an analysis of the circuit and determine the length of time it will take for the capacitor
to discharge through R4 from the upper switching threshold to the lower switching threshold .
Set this expression equal to 45 uS (see note below).
II.
Switch open
1. Perform an analysis of the circuit and determine an expression for the voltage at the common
node of R1, R2, and R6 (the voltage applied to the non-inverting input) in terms of VCC and the
resistor symbols . Set this expression equal to 0.75 VCC . We want this to be the case at the
instant that the capacitor voltage reaches the switching threshold, so set the capacitor voltage
equal to 0.75 VCC for this analysis step.
2. Perform an analysis of the circuit and determine the length of time it will take for the capacitor
to charge from the lower switching threshold to the upper switching threshold . Set this
expression equal to 55 uS . Note: Forming the thevenin equivalent of the circuit as seen by the
capacitor is the most straightforward way to perform this step. The thevenin resistance will be
equal to the value of R4 plus a contribution from the rest of the circuit (which was conveniently
shorted out when the switch was closed). Therefore, the RC time constant will be longer when
the switch is open than when the switch is closed, so we have allowed for a longer time for the
capacitor to charge up when the switch is open than to discharge when the switch is closed.
We now have five equations. Get creative, tweak some values, and find a solution. Below is a set of
standard values and the resulting voltages, currents, and intervals. You may wish to use these to test
your analysis equations.
R1 =
R2 =
R4 =
R5 =
R6 =
C=
75
82
43
3.3
36
1.0
k ohm
k ohm
k ohm
k ohm
k ohm
nF
f=
9879.15 hz
Switch Open
Vni =
11.289 v
Isw =
0.0
mA
Tch =
5.38-05 s
1-D
0.532
Switch Closed
Vni =
3.7519 v
Isw =
4.9122 mA
Td =
4.73E-05 s
D
0.468
Step 2 PWM/Error Processor
We will now develop a circuit that compares a
scaled version of the converter output voltage
(feedback) to a shifted and scaled version of the
triangle wave. Figure 3 shows the circuit, and
figure 4 shows the desired relationship between
the feedback signal and the triangle waveform. We
will develop a number of design constraints that
must be satisfied by the circuit element values
chosen.
Let’s assume the primary supply is 20 volts +/- 5
volts, and the converter is a boost converter producing 40 volts output (nominal). At 20 volts input, the
nominal duty cycle will be 50% for continuous conduction operation.
The signal applied to the non-inverting input of the
Figure 3 PWM processor
comparator (Vref) is a combination of our triangle
wave (reduced by an effective voltage divider
composed of R7, R8, and R9), plus an offset voltage
determined by the voltage divider consisting of R8
and R9. A 50% duty cycle at the PWM output will
result when the feedback voltage lies exactly 50%
of the way from Vref(min) to Vref(max), as shown on
Figure 4. As we can see, if the feedback voltage drops, the
Figure 4 PWM Timing
pulses will widen, increasing duty cycle and correcting the
voltage. Vice versa for a momentary increase in the output voltage. If the peak to peak amplitude of
Vref is small, a small change the feedback voltage will cause a large change in duty cycle, hence a large
“loop gain”. We’re not yet ready to decide exactly what Vref(min) and Vref(max) should be, but let’s
derive the relations for determining the proper resistor values when the time comes.
Write two circuit equations (1,2) for the two design constraints relating the max and min values of the
triangle wave (known) to Vref(max) and Vref(min), and the resistor values: R7 (known) , R8 and R9.
Step 3 Feedback Conditioning Network
We are designing the PWM error processor such that we get 100% duty cycle if the feedback control
voltage is below Vref(min), 0% if it is above Vref(max) (nominally), and varies linearly in the range
between. This is OK for a buck converter, but for a boost or buck-boost converter, 100% duty cycle will
cause saturation of the inductor and failure of the switching device. Therefore, we must add a feedback
conditioning circuit that will limit the maximum duty cycle to some reasonable value when the actual
converter output voltage (Vout) is too low, particularly during start up.
Let’s choose to allow the converter output voltage to vary +/- 3 volts (37 to 43 volts, again, subject to
tweaking) for active feedback of the loop (0 < D < 1). The curve below reflects this, with maximum duty
cycle limited to 90%.
Referring to the figure at the right, we see that if Vout is zero, the
diode will be reverse biased and the feedback control voltage will be
determined by the voltage divider consisting of R16 and R17, which
should be selected to yield approximately 90% duty cycle under this
condition. This represents another design constraint, and we may
write an equation (3) relating R16 and R17 to the appropriate
threshold voltage between Vref(min) and Vref(max) which will yield
90% duty cycle (refer to graph below).
The scaling of the voltage divider consisting of R18 and R19 must
provide a voltage 0.7 volts above the voltage determined by R16 and R17 at the anode of the diode
when Vout is at 37.6 Volts (10% of the way from 37 to 43 volts). When the output voltage reaches 43
volts and the diode is fully conducting, the resultant Feedback Control Voltage should equal Vref(max).
This represents two more design constraints (4,5), and we may write equations reflecting these
conditions .
VFBC
Vref(max)
DV
D V/10
VTHR
Vref(min)
0.0
0v
37 v
43 v
Vout
In addition, the parallel combination of R16 – R19 (consider the diode to be a short circuit when forward
biased) should present a resistance at the inverting input of the comparator that is approximately equal
to the resistance seen by the non-inverting input (parallel combination of R7 – R9)) in order to mitigate
input offset errors. This gives a sixth design constraint and an additional independent equation.
We have six equations, six unknown resistors, and two unknown voltages, which means we may choose
two of the unknowns and solve for the remaining six. If we choose Vref(min) and Vref(max), the
equations should be linear in terms of the conductances and may be solved by matrix inversion. Poor
choices of Vref(min) and Vref(max) will result in negative or very small conductances, so it may take some
iteration to get good values.
Step 4 Close the Loop
Connect your PWM to the boost converter module, and measure output voltage and Duty cycle for
input voltages from 17 to 23 volts with the heat lamp connected as a load. Repeat with two heat lamps
connected in series as a load.
Write-up requirements
1) Present each equation that you used to relate operating parameters to circuit elements, and
explain verbally how each equation relates to particular operating specifications.
2) Describe the solution method used to solve for the component values, and provide the values
yielded by the solution.
3) Based on the solution values, specify standard values to be used in circuit construction. Use
these values in your original equations and compute the operating parameters based on these
standard values. Compare these results to the desired operating parameters. Provide a
schematic showing all component values.
4) Build the PWM, measure the specified operating parameters, and compare to the desired
values. Record the necessary data and provide a graph of duty cycle vs. feedback voltage over
the range of feedback voltage which produces duty cycle ranging from zero to the maximum
limit.
5) Testing results with the boost converter module should include a graph of duty cycle and output
voltage vs supply voltage over the range described in Step 4. Compare your measurements with
the expected behavior as predicted by the theory (equations) governing the operation of a
boost converter. Include a schematic showing the connections to the boost converter module.