High-Performance Coherent Digital Sweep Oscillator
Using Piecewise Parabolic Interpolation
Ashraf Samarah and Otmar Loffeld
Center for Sensor systems (ZESS)
University of Siegen
Siegen, Germany
Email: samarah@ipp.zess.uni-siegen.de
Abstract-In this paper we propose an improved coherent
digital sweep oscillator with small size memory and extremely
low level of the spurious harmonic distortion in comparison
with the Pedersen sweep oscillator. This proposed system uses
the methodology of the piecewise parabolic interpolation.
Keywords- Spurious harmonic distortion; piecewise parabolic
interpolation; Coherent digital sweep oscillator; Spurious Free
Dynamic Range (SFDR)
I.
INTRODUCTION
Several applications require coherent sweep signals, i.e.
a sweep where both the phase and frequency must be
specified for all time. Examples of such applications are
target velocity estimation [1], phase coding of sweep signals
in communication applications, system characterization,
radar, especially in Synthetic Aperture Radar (SAR), sonar,
acoustic digital imaging, and the determination of system
response with network analyzers [2, 3].
There are only a few methods for generating coherent
sweep signals. One method is to store in high-speed digital
memory a predetermined waveform, such as coherent
sweep. The main limitation is the time-bandwidth product.
Another approach is based on the calculation of binary
words [4] , corresponding to the analytical expression of the
quadratic phase of a sampled linear sweep. These
calculations must be performed in real time; and as a draw
back, the maximum attainable frequency will only be in the
kilohertz range. For these reasons, an improved structure
minimizing memory size and the level of the spurious
harmonic distortion is presented here.
II.
PEDERSEN SWEEP OSCILLATOR
A method for the generation of digital sweep signals was
proposed in 1990 by Pedersen [3]. His approach is based on
real time digital evaluation of the phase of the desired swept
signal, and then reading its value from a look-up-table
(LUT) of length L( L  2 K ) . Pedersen’s approach presented a
method for the generation of coherent sweep signals, based
on a digital approach which minimizes the restrictions of
current techniques, i.e., limited frequency range or limited
signal duration. The digital sweep system performs the
following functions: i) real time generation of the phase of a
linearly swept signal, ii) extraction of mod( 2 ) from the
total phase; and iii) generation of the desired sine or cosine
swept signals by means of a look-up table. Let w(t ) is the
instantaneous frequency of a linearly swept signal with start
frequency of w1 and sweep rate of S (Hz/s). w(t ) is given
as:
w(t )  2 St  w1
(1)
The corresponding instantaneous phase is obtained by
integrating (1):
 (t )   St 2  w1t  0
(2)
 (t ) contains a quadratic term corresponding to the linearly
varying frequency (the sweep rate, S), a linear term
corresponding to the start frequency, and a constant
term, 0 corresponding to the start phase. The generation of
the coherent digital sweep signal is started by double
integration for the constant sweep rate in the time domain to
obtain (1) and (2), then the extraction of mod (2π) from the
total phase, and then the generation of the desired sine or
cosine swept signals by means of the look-up-table. The
main disadvantages of Pedersen’s sweep oscillator are the
high level of spurious harmonic distortion and the large
memory size. The approach is well documented in [3].
III. DIRECT DIGITAL FREQUENCY
SYNTHESIZER AND NEW COMPRESSION
TECHNIQUE
A Direct Digital Frequency Synthesizer, commonly
referred to as DDFS, is used to generate the reference
frequencies whenever extremely precise frequency
resolution and fast switching speeds are required, and the
DDFS is an essential and important technique to play this
role. The most common DDFS architecture is the Tierney,
Radar, and Gold architecture [4], and it is well documented
in [5-7]. The ROM compression techniques are also
essential, since a straight forward implementation, of the
look-up table for the sine function, requires more than 4
Giga samples of storage for a phase accumulator resolution
of 32 bits and output resolution of 12 bits. However,
compression techniques inevitably lead to degradation in the
spectral purity of the generated sine wave.
DDFS synthesizes a sine wave by using a periodically
overflowing phase accumulator to generate and store the
phase information, DDFS also uses a ROM based look up
table to compute the sine function, as shown in Fig.1. The
frequency of the generated sine wave is controlled by the
Frequency Input Word (FIW). Equation (3) presents the
frequency relations of a DDFS structure.
f min 
f clk
2L
0  FIW  2 L 1
f out  f min.FIW
(3)
where f min is the minimum synthesizable frequency, f clk
is the clock frequency, L is the word length of the phase
accumulator, f out is the output frequency, FIW is the
frequency input control word.
FIW
Phase Accumulator
Register
clk
 (n)
W
Computation
of
sin(2
 (n)
2L
)

i  I1
x(mk  i )Ts  hI (i   k )Ts 
y (k ) 
I2

N
x(mk  i )
i  I1

I2
  bn (i) x(mk  i)

(6)
i  I1
 kn v(n),
n0
v ( n) 
I2
 bn (i) x(mk  i)
i  I1
Technically, the sine wave is divided into four basic
quadrants; each quadrant is subdivided into sections. By
exploiting the symmetry of the sine/cosine wave, only the
parameters that are relevant to one quadrant need to be
stored, instead of storing values of the sine function directly
in the ROM as in the traditional methods, the interpolation
coefficients will be stored. The Farrow structure as in [13]
receives input samples from the sine wave and performs the
interpolation based on the neighboring three points. Thus,
for each base point (sample of the sine), three interpolation
coefficients are computed [V1, V2, V3]. These interpolation
coefficients are used according to (6) to compute the value
of the sine wave at any arbitrary fractional delay specified
by  k . For parabolic interpolation we have:
y(k )  V1 (2)  kV2 (2)  k 2V3 (2)
(7)
where  k is the fractional shift, n is the base point index
and k is the fractional delay index. The interpolation
calculation has been pre-computed for a specified number of
base points (sections) of the sine wave and stored in a ROM.
Each word in the ROM consists of [V1, V2, V3] which in
conjunction with the fractional delay  k can be used to
calculate intermediate points between two base points[11].
IV.
where x(m)is a sequence of signal samples taken at
interval Ts ,  k is a fractional shift, mk is the base point
index, and hI (t ) is a finite-duration impulse response of a
continuous time analog interpolating filter. The Farrow
implementation assumes that the impulse response is a
 bn (i) kn
n0
 kn
N
(4)
(5)
The coefficients bn (i ) are fixed numbers, independent
of  k , determined by the filter's impulse response hI (t ) .
These coefficients are chosen to provide the widest passband and the strongest attenuation at multiples of the
sampling frequency. We can consider y(kTi )  y(k ) , after
we substitute (5) in (4) and rearrange terms to show that the
interpolation can be performed by:
n0
y (kTi )  y(mk   k )Ts 
N
 bn (i) kn
n 0
N
DDFS is inherently as frequency stable as the reference
clock. It provides numerically highly linear frequency
tuning with controllable frequency resolution. A simple
implementation of DDFS uses a ROM lookup table to
calculate the trigonometric functions. Unfortunately, in spite
of memory saving, due to both of the phase truncation and
quadrant symmetry, a large lookup tables are needed
because they slow down the DDFS’ operations and increase
the power consumption. Hence, many ROM compression
techniques [8-10] aimed to reduce the lookup table size,
since the straight forward implementation of the sine
function look-up table requires more than 4 Giga samples of
storage for a phase accumulator resolution of 32 bits and
output resolution of 12 bits.
Eltawil and Babak [11] and David De Caro [12]
proposed an architecture, which employs a second and
higher order interpolations functions to further compress the
ROM size, while maintaining or exceeding the spectral
purity of the techniques mentioned above, with minimal
hardware overhead. Eltawil's architecture depends on a
piecewise parabolic Farrow structure [13] due to its
hardware efficient implementation and good performance.
The fundamental equation for digital interpolation of
data signals is as follows:

hI (t )  hI (i   k )Ts  

Synthesized
Digital
Sine
Figure 1. DDFS Architecture
I2
piecewise defined polynomial in each Ts segment with
i  I1 , I 2  .
THE PROPOSED DIGITAL SWEEP
OSCILLATOR
The proposed system is a hybrid of the digital sweep
generator and the system using interpolation based direct
digital frequency synthesis. The interpolator uses
predetermined interpolation coefficients to fit the sine wave
from the calculated phase instead of using a predetermined
waveform stored in a big sized memory. This implies that a
smaller look-up table for the sine and cosine functions is
used compared to existing architectures with minimum
hardware overhead, and the computation of the sinusoidal
values is performed by a piecewise parabolic and extended
by a piecewise-polynomial approximation or interpolation
structure. Thus only interpolation coefficients are stored in
the memory. Fig.2 shows the block diagram of the proposed
sweep oscillator.
In this sweep generator the start and end frequency can
be controlled by the initial content of the counter and the
accumulator. Furthermore, the sweep rate can also be
controlled by the location and size of the address lines. The
coherent digital sweep oscillator uses the clock to trigger the
counter (first integrator) and feeds the output to the
accumulator (second integrator). In general, the phase of the
sweep signal is not equal to the value of the phase stored in
the accumulator because only a subset K of the output lines
from the accumulator is sent to the look-up table.
Start Frequency
Preset
Counter
Clock
O/P
Digital-to-Analog
Converter
:36 line bus
Start Phase
Preset
Figure 3. The block diagram of the simulated structure
works instead of Farrow structure to generate the sine wave.
Regarding to this equation, the simulated structure
generates four interpolation coefficients for each section,
for example if we divided the quarter of the sine wave to
three sections, we will get 3x4=12 interpolation
coefficients, etc. Based on (8), our implementation
improves the system which was reported in [10] to
decrease the error; this is done when we increase a
quadratic equation to become a cubic equation.
Consequently, four interpolation coefficients will be
generated and appear instead of three coefficients.
Accumulator
Polynomial
Evaluation Unit
: 8 line Bus
V.
Figure 2. Block diagram of the proposed sweep oscillator
y (n, k )  V1(n)  kV2 (n)  k 2V3 (n)  k 3V4 (n)  ...
(8)
where  k is the fractional shift, n is the base point index,
and k is the fractional delay index.
The simulations were done by simulating Fig.3 within
Fig.2 to realize the polynomial evaluation unit; in these
simulations we considered 8 least significant bits from the
accumulator as the address lines to the polynomial
evaluation unit shown in Fig.2 which contains the memory.
The minimum and maximum values of these 8 bits are 0 and
255 in decimal value, respectively. The encoded 8-bit output
from the accumulator is defined to feed the memory in the
polynomial evaluation unit to represent a phase between 0
and 2 radians; 0 corresponds to 0 [rad] and 255 correspond
to (255/256) × 2 rad. The simulation’s settings have a
wide flexibility in our implementation.
Fig.4 shows our generated coherent digital sweep signal.
The resulting SFDR (Spurious-Free Dynamic Range) is 95.6
dBc with 16 sections per quadrant and it is depicted in Fig.5.
Volts
Al-Ibrahim in [14] presented an efficient architecture
with low level spurious harmonic distortion. The drawback
of his architecture is inherited in the relatively large size of
its ROM and the complexity of the implementation. On the
other hand our architecture accomplishes the generation for
the coherent digital sweep signals, with low level of the
spurious harmonic distortion, low cost in complexity, and
smaller size of ROM.
The new architecture is shown in Fig.3. It uses the
Farrow structure[11] to generate the interpolation
coefficients. The output of this interpolation based sweep
generator is comparable with other methods that implement
the look-up table method. Alternatively, the size of the
ROM is reduced by a factor of more than 128 times with
respect to the one in Pedersen’s approach, when using 12
address lines and 15 bits word size. Then again, we increase
the performance of our architecture by using a higher order
interpolation instead of using a second order interpolation
only. This is easily controllable by our Matlab simulation.
As we will see later when we increase the number of
interpolation coefficients the error will be decreased further.
Equation (8) is a polynomial equation derived from (7); for
cubic and higher order interpolations:
SIMULATION’S RESULTS
Time (s)
Figure 4. The generated coherent swept signal by the new
technique (2 periods)
Amplitude dB
Frequency (Hz)
Figure 5. Output spectrum with 16 sections
Table 1 shows the comparison between our architecture
and other techniques with respect to the ROM size and
SFDR.
TABLE I. COMPARISON BETWEEN THE
TECHNIQUES BASED ON THE ROM SIZE AND SFDR
Architecture
Our proposed system
Curticapean [8]
Nicholas [10]
Eltawil [11]
ROM size
(bit)
480
832
3072
600
SFDR (dBc)
95.6
85
90.3
80
Figure 7. Spectrum of sweep signal using the interpolation method
(Order=2, s=4)
The size of the look-up table in Pedersen‘s oscillator is
61440 bits, while the size of the LUT of the interpolator is
reduced to 480 bits. (That means our architecture achieves a
compression ratio that reaches 128). The error also will be
decreased by increasing two parameters; the number of
sections per quadrant (S), and the order of the interpolation
equation. The modified sweep oscillator still has smaller
size than the one in Pedersen sweep oscillator, and this is
shown clearly in Fig.8 and Fig.9.
Amplitude dB
Amplitude dB
Fig.6 and Fig.7 illustrate the spectra of the sweep signal
using different orders and number of sections.
4
Frequency (Hz)
Figure 8. Error Spectrum (order=1 with different number of
sections/quad)
Frequency (Hz)
Figure 6. Spectrum of sweep signal using the interpolation method
(Order=1, S=4)
[9]
Order=3
[10]
Amplitude dB
[11]
[12]
[13]
[14]
4
Frequency (Hz)
Figure 9. Error Spectrum ( order=3 with different number of
sections/quad)
VI.
CONCLUSIONS
A new technique was proposed to generate sinusoidal
waves based on a piecewise parabolic interpolation utilizing
the Farrow structure to generate the interpolation
coefficients.
The proposed sweep oscillator shows an extremely low
level of the spurious harmonic distortion and at the same
time reduces both the hardware complexity and memory
size of the LUT. The new size of the ROM is reduced by a
factor of more than 128 when using 12 address lines and 15
bits word size. This sweep signal generator is seriously
comparable with other methods that implement the look-up
table method.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
J. E. Wilhjelm and P. C. Pedersen, "Target velocity estimation
with FM and PW echo ranging Doppler systems-Part I: system
analysis," IEEE Trans. Ultrason. Ferroelectr. Freq. Control,
vol. 40, pp. 373-380, 1993.
R. G. Plumb, and Ma, H, "Swept frequency reflectometer design
for in-situ permittivity measurement," IEEE Trans.
Instrumentation. Measurement, vol. 42, pp.730-734, 1993.
P. C. Pedersen, "Digital sweep generator," in U.S. Patent
Application, 1988.
R. C. Tierney J, Gold BA, "Digital synthesizer," IEEE Trans.
Audio and Electro acoustics, vol. 19, pp. 48-57, 1971.
A. L. Bramble, "Direct Digital frequency synthesize," in
proceedings of the Thirty Fifth Annual Frequency Control
Symposium, 1981, pp. 406-414.
T. A. K. D.P. Noel, "Frequency Synthesis: A comparison of
techniques," in Proceedings of Canadian Conference on
Electrical and Computer Engineering, Canada, 1994, pp. 535-8.
H. S. L.K. Tan, "200 MHz quadrature digital synthesizer /mixer
in 0.8um CMOS," IEEE Journal of Solid-State Circuits, vol. 30,
pp. 193-200, March 1995 1995.
K. I. p. a. J. N. F. Curticapean "Direct digital frequency
synthesizer with high memory compression ratio," Electron.
Lett., vol. 37, pp. 1275-1276, 2001.
F. C. a. J. Nittylahti, "Hardware efficient direct digital frequency
synthesizer” in ICECS'01. vol. 1, C. Proc IEEE Int. Conf.
Electron., Syst., Ed., 2001, pp. 51-54.
H. T. N. I. a. H. Samueli, "A 150-MHz direct digital frequency
synthesizer in 1.25-micron CMOS with -90-dB spurious
performance," IEEE Journal of Solid-State Circuits, vol. 26, pp.
1959-1969, Dec.1991.
A. M. Eltawil. and D. Babak, "Interpolation based direct digital
frequency synthesis for wireless communications" in
Proceedings of the IEEE Wireless Communications and
Networking Conference (WCNC). vol. 1, 2002, pp. 73-76.
D. D. C. a. A. G. M. Strollo, "High-Performance Direct Digital
Frequency
Synthesizer
Using
Piecewise-Polynomial
Approximation," IEEE Trans. on Circuits and Systems, vol. 52,
pp. 324-337, Feb, 2005.
R. M. G. L. Erup, and R.A. Harris, "Interpolations in digital
modems Part II: Implementation and Performance," IEEE
Trans. Comm., vol. 41, pp. 998-1008, 1993.
M. M. Al-Ibrahim, "A New hardware efficient coherent digital
sweep oscillator with very low sweep rates and harmonic
distortion" Electrical Engineering, vol. 84, 2002.