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EPE 2005 Dresden
ESCAPEE
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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The achievements of the EC funded project "Establish
Silicon Carbide Applications for Power Electronics in
Europe" (ESCAPEE)
J. Millan1, P. Godignon1, D. Tournier1, P.A. Mawby2, S. Wilks2, O.J. Guy2, and
L. Chen2, R. Bassett3, A. Hyde3, N. Martin4, M. Mermet-Guyennet4, S.
Pasugcio4, S. P M. Syväjärvi5, R.R. Ciechonski5, R. Yakimova5, L. Roux6,
F. Torregrosa6, T. Bouchet6, J-M. Bluet7, G. Guillot7, D. Hinchley8, S.
Jones8, J. Rhodes8, P. Taylor9 and P. Waind9
1Centro Nacional de Microelectrónica, Campus Universidad Autónoma de
Barcelona, 2School of Engineering, University of Wales Swansea,
3ALSTOM Research & Technology Centre, 4ALSTOM Transport SA,
5Department of Physics and Measurement Technology, Linköping
University, Sweden, 6Ion Beam Services, 7Institut National des Sciences
Appliquées de Lyon, Laboratoire de Physique de la Matiere CNRS,
8Semelab Plc, 9Dynex Semiconductor Ltd.
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Overview
• Overview of recent results from the ESCAPEE project.
• Update to the information originally presented at EPE 2003 in
Toulouse.
• Key targets
• Significant scientific progresses
• Final achievements and successes.
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Key research targets
(creation
and introduction of SiC technology, from fundamental
science through to real applications.)
• Produce improved quality of thick (>10m) SiC epi-layer
material suitable for high power devices.
• Develop device processing and fabrication technology
(implantation, passivation, etching, metallization).
• Establish edge termination to enable high voltage applications.
• Develop high temperature device packaging suitable for SiC
• Use the created technology in a module introduction and enduser application in traction systems
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Important scientific progresses
Significant results from the ESCAPEE project include:

Development of new sublimation epitaxial growth technique - produces epilayers at growth rates up to 20 times faster than standard CVD growth.

Development of high temperature implantation equipment for SiC and the
subsequent commercialisation.

Development of surface cleaning processes and reduction of surface
damage produced by high temperature annealing, for implant activation.

Development of low resistance n-type and p-type ohmic contacts and high
quality Schottky diodes.

Design of edge termination and fabrication of thermally stable Schottky
diodes with blocking voltages of up to 4.7kV and reverse leakage currents
of less than 2e-7 A/cm2 at 3.5kV.

Increased device yield of 1.6mm 1.6mm diodes from 12% to 43% using a
novel polishing technique.
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Significant results from the ESCAPEE project continued…

Development of 1.2 kV MOSFETs.

Record Field-effect mobility and drain current as a function of gate
voltage for transistors with a PVT grown epilayer and a reference CVD
grown epilayer.

Design and production of specialized high temperature thermally stable
packaging for high voltage SiC devices.

Production of a demonstrator module using SiC diodes and Si IGBTs.
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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ESCAPEE Technological developments
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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ESCAPEE’s results – Material
Fast epitaxy by PVT
•Sublimation of a solid source and transport of vapor to a substrate
•ideas based on the sublimation growth process to produce wafers but
smaller distance between source and substrate
•Benefit of high growth rate from intrinsic sublimation to yield thick layers
•Develop growth conditions to achieve smooth surfaces and low doping
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Achievements
• Low doping in the E15 range has been
achieved
• Causes for the background doping are
known and even lower doping is
expected
0,04
250
PVT
PVT, I
200
D
0,03
150
0,02
CVD, I
CVD
D
100
0,01
50
tox = 1550 Å,
L = 20 m, W= 100 m
0
-5
0
5
10
15
20
25
0
30
• Higher field-effect mobility and drain
current for transistors with a PVT grown
epilayer than on reference CVD grown
epilayer.
• A patent on the fast PVT epitaxy
technology has been filed
• Discussions with partners for
commercialization are in progress
Gate voltage [V]
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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ESCAPEE’s results – Implantation
High temperature implanter
High temp chucks :
- Several versions available and already sold (Univ. Madrid, INRS Canada, LETI.)
V2 : Installed in Madrid
SiC Workshop. EPE 2005, September 12
Proto of V3 : Installed at INRS (Canada)
ESCAPEE Project
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Novel process technological step
• Results using Graphite cap – surface protection process are
promising.
Photoresist
Carbon
750°C Anneal (Ar)
SiC
SiC
RIE
• Carbon cap produced by annealing photoresist
under argon (750°C)
• Anneal sample as before (1600° for 30 min)
• Remove Carbon Cap (RIE with O2)
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
SiC
12
Surface roughness reduced by up to a factor of 10
Improved forward I(V) characteristics
Improved reverse leakage currents
(a)
Not protected
SiC Workshop. EPE 2005, September 12
(b)
C-cap protected
ESCAPEE Project
Carbon cap experiment
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1.2 kV SCHOTTKY DIODES
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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1.2 kV Schottky Diodes – Area dependence and wafer uniformity
ESC12 - AsDep
1
0,75
0,1
Forward current (A)
Forward current (A)
1,00
0,01
1E-3
1E-4
1E-5
1E-6
1E-7
1E-8
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
Forward voltage (V)
0,50
0,25
0,00
0,0
ESC12 - AsDep
2
0.4 x 0.4 mm
2
0.8 x 0.8 mm
2
1.6 x 1.6 mm
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
Forward voltage (V)
Forward mode I(V) curves at 350ºC for various device area
I(V) uniformity:
Thickness and doping OK
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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1.2 kV SCHOTTKY DIODES - Yield
Manufacturing yield versus Chip size and wafer
micropipes density
Yield (%) = exp (Area * D)
100
Escapee
samples
90
80
Escapee
samples
70
60
1/cm
2
5/cm
2
2/cm
2
16/cm
2
2
30/cm
Unpolished
Polished
ESC12_UnPolished
50
Escapee
samples
40
0,5
1,0
1,5
2,0
Chip size (mm x mm)
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
2,5
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Discrete Package
• New package uses DBC baseplate,
eliminating separate copper
baseplate and DBC substrate used in
the conventional isolated TO257.
• Offers reduction in weight, improved
reliability and the potential to operate
at elevated temperatures.
• Package successfully used to
characterise 1000V ESCAPEE
diodes at 225°C.
• Limited VR to 800V during hot test to
avoid destroying devices.
DBC TO-257 Package
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Diode Characterisation
Packaged devices show little area dependence and better stability and
during device testing
Diode Forward Characteristics
SiC Workshop. EPE 2005, September 12
Diode Reverse Characteristics
ESCAPEE Project
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High-Temperature Operation
12
1E-02
25°C
125°C
225°C
10
IR (A)
IF (A)
8
1E-03
1E-04
6
4
1E-05
2
1E-06
0
0
1
2
3
4
5
25
75
VF (V)
Diode Forward Characteristics
SiC Workshop. EPE 2005, September 12
125
TJ (°C)
175
225
Diode Reverse Characteristics (at 800V)
ESCAPEE Project
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1.2 kV SCHOTTKY DIODES – switching T dependence
Temperature dependence on the dynamic behavior
of the 2.16 mm2 SiC SBD
 No significant impact of temperature on switching
characteristics
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Compact modelling
ESCAPEE’s results
8
3.00E+02
Ultra-fast Si PiN diode
2.50E+02
ESCAPEE SiC Schottky
6
ESCAPEE model
4
1.50E+02
I (A)
J (A/cm2)
2.00E+02
2
SM d34 T=300K
1.00E+02
SM d34 T=473
0
0.0E+00
SM d34 T=573K
5.0E-08
1.0E-07
1.5E-07
JA d34fb25
5.00E+01
JA d34fb 473
-2
JA d34fb 573
0.00E+00
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-4
Temperature (K)
Time (s)
DC
SiC Workshop. EPE 2005, September 12
Switching
ESCAPEE Project
2.0E-07
2.5E-07
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1.2KV Hybrid Module
• Aerospace IGBT/diode halfbridge module.
• 150A 1200V Infineon Silicon
IGBT.
• Four 1.6x1.6mm 1000V
ESCAPEE SiC Schottky Diodes
in parallel.
• AlSiC Baseplate, Al/AlN
substrate, Cu lead-frame, PBT
ring-frame and lid.
• PbSnAg solder and vacuum
furnace die-attach.
• 5mil/12 mil Al wire-bonds.
SiC Workshop. EPE 2005, September 12
Si IGBT/SiC diode hybrid
module with lid removed
ESCAPEE Project
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Hybrid Module Characterisation
60
50
40
IF (A)
• Three IGBT/diode substrates
exhibited IR<300uA at 1000V.
• One IGBT/diode substrate
suffered fractured breakdown
characteristic above 600V.
• VF < 3V at 50A, 25°C.
• Module successfully switched
25°C, 50A, 600V, 500A/us.
30
20
10
0
0
0.5
1
1.5
VF (V)
2
2.5
Hybrid Module SiC Diode Forward
Characteristics
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Hybrid Module Switching
ESCAPEE’s results
Si IGBT/SiC diode hybrid module inductive-load
switching at 25°C, 50A, 600V, 500A/us.
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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3.5 kV SCHOTTKY DIODES
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Diodes fabrication for module
1,6 x 1,6 mm2
• Good current density uniformity vs diodes size
• RON= 40m.cm2 close to theoretical expected
value (31m.cm2).
Reverse Current (A)
• 4.5 kV ESCAPEE Schottky diodes fabricated
at CNM for hybrid module
Id
1E-5
1E-6
1E-7
1E-8
1E-9
1E-10
1E-11
•Very low reverse leakage current density
(JR<10 µA/cm2 @ 3.5kV)
• No breakdown differences between
measurements made in the air and inside
galden on polyimide passivated devices.
-3000
-2000
-1000
Schottky diode reverse characteristics
0.4x0.4
0.8x0.8
1.2x1.2
1.6x1.6
50
40
30
20
RON = 40 m.cm2
B = 0,74ev
10
0
0,0
0,5
1,0
1,5
2,0
2,5
Voltage (V)
4.7kV Breakdown voltage measured =
termination efficiency of at least 80%
SiC Workshop. EPE 2005, September 12
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Reverse voltage (V)
Current density (A/cm2)
• Ni used as Schottky contact - stability
demonstrated up to 200°C
-4000
Schottky diode forward
characteristics versus size.
ESCAPEE Project
3,0
26
4.5 kV- 8A Module fabrication
• Power Modules have been constructed
integrating Si IGBTs and SiC Schottky diodes
in chopper configuration
Arm electrical equivalent
circuit, packaged diodes
3D-High voltage
module CAD view.
• High voltage 4.5 kV SiC diodes have been
successfully assembled with high-voltage Si
IGBTs into modules and characterized by
Dynex Semiconductor.
High voltage packaging
technology successfully applied to
Si/SiC hybrid module fabrication
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Module characterisation
IF (20ºC)
104
IF (125ºC)
12
78
8
52
4
26
0
JF(A) (per die)
IF(A) (module)
16
0
1
2
3
4
5
6
VF(V)
• The measured on-resistance of the
diode is lower and nearer to the
theoretical value when measured on
packaged devices.
• SiC Schottky diodes show excellent
behaviour in forward mode up to
125ºC
Schottky diode forward characteristics.
Module I(V) left, Die J(V) right, at 20ºC
and 125ºC
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Module characterisation
Diode arm IGBT arm
Forward 20 °C
50A/cm2
@ VF=3V
Forward 125 °C 26A/cm2
@ VF=3V
Reverse
@3.1 kV, 20°C
8µA
3µA
• very low leakage current
values have been measured at
3.1kV (curve tracer limit) in the
reverse mode.
• diode arm leakage current
(8µA @ 3.1kV) is in the same
range than that of the Si-IGBT
arm.
Experimental SiC-Schottky diode and Si-IGBT
modules forward characteristics and reverse
leakage current at 3.1kV reverse bias.
SiC Schottky diode leakage current level
compatible with Si-IGBT
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Module dynamic switching
Dynamic switching has been performed at 125°C
30
25
1500
VCE (V)
IC (A)
20
15
10
VCE (RG=2.2)
VCE (RG=7.5)
VCE (RG=15)
VCE (RG=30)
2000
IC (RG=2.2)
IC (RG=7.5)
IC (RG=15)
IC (RG=30)
35
1000
500
5
0
-5
10µ
11µ
12µ
13µ
14µ
time (s)
Current waveform versus gate
resistance at 125°C (VCE=1.8kV)
0
10µ
11µ
12µ
13µ
14µ
time (s)
VCE fall time versus gate resistance at 125°C
• 10A, 1800V switching at 125°C
• 4.5kV-8A SiC-Schottky diodes allow significant switching loss
reduction and higher temperature working operation in
comparison
to Si-PIN
diodes
SiC Workshop.
EPE 2005,
September 12 ESCAPEE Project
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Power MOSFET Fabrication
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Gate oxide capacitances
Interface density state in the SiC gap near the conduction band
13
100 nm TEOS
-2
-1
Interface Density States [cm eV ]
10
12
10
TEOS + RTA N2O
O2 + TEOS +O2
TEOS + N2
N2O + TEOS
O2 + TEOS + Ar
11
10
0.15
0.20
0.25
0.30
0.35
EC-ET [eV]
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
0.40
32
Lateral N-MOSFET test structure
N-MOSFET on 4H-SiC: Thermal N2O /100nm TEOS / 950ºC O2
60
1,5
Drain Current [mA]
2
Vg=10V
Effective Mobility eff [cm /Vs]
Channel mobility vs gate bias
50
1,0
Vg=8V
Vg=6V
0,5
Vg=4V
Vg=2V
0,0
0
1
2
3
4
5
Drain-Source Bias [V]
40
30
N2O + TEOS
20
Thermal Oxide
10
0
-4
-2
0
2
4
6
Gate Bias [V]
• Current higher than usual (x4 compared to LiU S230)
• Threshold voltage: in the range –1V / 0.5V ( short/long channel)
• Channel mobility: 40- 45 cm2/Vs (on epilayer layer annealed at 1600ºC)
• Stable up to 15V
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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10
12
14
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ESCAPEE CURRENT STATUS:
1.2 kV Schottky diodes process stable with good yield
3.5 kV Schottky diodes process repetitive: yield depends on wafer quality
Gate dielectric with channel mobility on implanted layer: 50 cm2/Vs
1.2 kV and 3.5 kV Power MOSFETs in processing
SiC Workshop. EPE 2005, September 12
ESCAPEE Project
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Si/SiC hybride modules
SiC Workshop. EPE 2005, September 12
ESCAPEE Project