Multi-level Logic Synthesis
1
Zvi Kohavi and Niraj K. Jha
Logic Synthesis
Technology-independent: Optimize circuit for targeted design objective
using laws of Boolean Algebra
• Example objective: minimize area under a delay constraint
• Apply following logic transformations iteratively: preserves input/output
behavior of circuits
– Factoring
– Decomposition
– Extraction
– Substitution
– Elimination
Technology-dependent: map resultant circuit to a library of gates available
for the given semiconductor technology
2
Factoring
Factoring: converts a sum-of-products expression to an expression with
multiple levels without introducing any subfunctions
Factored form: a recursive sum-of-products representation
Example: Factor f = uvxz + wxz + u’y’z + v’x’z’ + v’yz’
u
v
w
f = uvxz+wxz+u y z+v x z +v yz
x
y
z
(a) Network graph for sum of products.
u
v
x
z
w
x
z
u
v
w
f = z(x(uv+w)+u y )+(x +y)v z
x
y
z
(b) Network graph for factored expression.
u
v
w
x
z
u
y
u
y
z
f
x
y
v
x
z
f
v
z
v
y
z
(c) Two-level circuit.
(d) Multi-level circuit.
Literal-count of factored form: 11 (reduced from 16)
3
Decomposition
Decomposition: replaces a factored switching expression with a set of new
expressions
Example: Factored expression f = z(x(uv + w) + u’y’) + (x’ + y)v’z’ can be
decomposed as
f1 = uv + w
f2 = x’ + y
f3 = v’z’
f4 = xf1 + u’y’
f = f2f3 + zf4
u
f1 = uv+w
v
f4 = xf1+u y
w
x
y
f2 = x +y
z
f3 = v z
f = f2f3+zf4
Literal-count: 15
4
Extraction
Extraction: extracts common subexpressions from two or more
expressions in factored form
Example: Consider
f1 = (uv + w)x + u’y’
f2 = (uv + w)z
• After extraction:
f1 = f3x + u’y’
f2 = f 3 z
f3 = uv + w
u
v
w
x
y
f1 = (uv+w)x+u y
u
v
w
f3 = uv+w
f1 = f3x+u y
x
f2 = (uv+w)z
z
(a) Network graph before
extraction.
y
f2 = f3z
z
(b) Network graph after
extraction.
Literal-count: reduces from 10 to 9
5
Substitution
Substitution: replaces a subexpression in expression f with a variable g
corresponding to a node in the network graph
• g is substituted into f, or
• f is expressed in terms of g
Example: Consider
f1 = uvx + wx + u’y’
f2 = uv + w
• After substitution:
f1 = f2x + u’y’
u
v
w
x
y
f1 = uvx+wx+u y
u
v
f1 = f2x+u y
f2 = uv+w
w
x
y
f2 = uv+w
(a) Network graph before
substitution.
(b) Network graph after
substitution.
Literal-count: reduces from 10 to 7
6
Elimination
Elimination: eliminates an internal node from the network graph
Example: Consider
f1 = x + f 2
f2 = y + z
• After elimination: if f2 not needed elsewhere
f1 = x + y + z
Literal-count: reduces from 4 to 3
7
Techniques for Factoring
Algebraic expression: no implicant of the expression contains another
implicant
Example: x + yz
Boolean expression: an expression that does not satisfy above condition
Example: x + xy
Operations on algebraic expressions simpler: can be treated similarly to
multiplication and division of polynomials
• Disadvantage: prevents exploitation of all laws of Boolean Algebra
– Idempotency, dual of distributivity [x + yz = (x + y)(x + z)], and
absorption cannot be used as they do not have an analog in
conventional polynomial algebra
– Complementation (x + x’ = 1 and xx’ = 0), involution and De Morgan’s
theorem cannot be used since complements are not defined in
polynomial algebra
– Complemented literals are deemed to be unrelated to
uncomplemented literals
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Algebraic Factored Form
Factored form:
• Algebraic if multiplication of its terms yields an algebraic sum-of-products
expression without the use of above-mentioned laws
• Boolean otherwise
Example: Factored form (w+x)(y+z) is algebraic since wy + wz + xy + xz is
algebraic
Example: Factored form (w + yz)(x + yz) is not algebraic, but Boolean,
because wx + wyz + xyz + yzyz is not algebraic
• yzyz cannot be simplified because idempotency cannot be used
• This term is not allowed to absorb xyz since absorption law is not allowed
Example: (x + y)(x’ + z) is not algebraic since multiplying it out gives xx’
which cannot be simplified further
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Division Operation
Division operation: f = fdfq + fr
• fd: divisor
• fq: quotient
• fr: remainder
Algebraic division: if fd and fq have no variables in common
• Else, Boolean division
• fd: correspondingly an algebraic or Boolean divisor
• If fr = 0: fd correspondingly an algebraic or Boolean factor
Example: Let f1 = vx + vy + wx + wy + z = (v + w)(x + y) + z
• Algebraic divisor: (v + w)
• Quotient: (x + y)
• Remainder: z
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Division Operation (Contd.)
Example: Let f2 = vx + vy + wx + wy = (v + w)(x + y)
• Algebraic factors: (v + w), (x + y)
Example: Let f3 = w + xy + z = (w + x)(w + y) + z
• Boolean divisors: (w + x), (w + y)
Example: Let f4 = w + xy = (w + x)(w + y)
• Boolean factors: (w + x), (w + y)
Example: Let f5 = xy + xz + yz
• Factored form 1: x(y + z) + yz
• Factored form 2: (x + y)z + xy
• Factored form 3: (x + z)y + xz
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Algebraic Kernels and Co-kernels
Cube-free expressions: one that cannot be factored by a cube
Example: wx + yz is cube-free
Example: xy + xz is not cube-free since it can be factored by x
Example: xyz is not cube-free since it can be factored by its literals
Kernel and co-kernel: if an expression divided by a cube results in a cubefree quotient, then the quotient is called a kernel and the cube the
corresponding co-kernel
• Level-0 kernel: a kernel that has no kernel except itself
• Level-n kernel: has at least one kernel of level n-1, but no kernel of level n
or greater except itself
• Co-kernel level: same as its kernel’s
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Kernels and Co-kernels (Contd.)
Example: f = uwz + uxz + vwz + vxz + yz + uv
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Rectangle Covering
Consider a sum-of-products expression f with p cubes and q distinct literals
p x q cube-literal incidence matrix: element (i,j) = 1 if jth literal used in the
ith cube, and 0 otherwise
Rectangle (r,c) of matrix: set of rows r and columns c in which all entries
are 1
• (r1,c1) contains (r2,c2) if r1 r2 and c1 c2
Prime rectangle: a rectangle not strictly contained in another rectangle
Co-rectangle of (r,c): (r,c) where c is the complement of column subset c
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Rectangle Covering (Contd.)
Example: Let f = uwz + uxz + yz + uv
• It has four cubes and six distinct literals
• Cube-literal incidence matrix:
• Prime rectangle: ({uwz,uxz}, {u,z})
– Co-kernel: uz
– Co-rectangle: ({uwz,uxz}, {v,w,x,y})
» Kernel: w + x, obtained by restricting uwz + uxz to literals in
{v,w,x,y}
• Other prime rectangles: ({uwz,uxz,uv}, {u}), ({uwz,uxz,yz}, {z})
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A Factoring Approach
Start with a sum-of-products and derive a factored form to reduce literalcount:
• Let f = fdfq + fr
• Recursively factor fd, fq, and fr into their factored forms until these forms
cannot be factored any more
• Extract any common subexpressions from the quotient and part of the
remainder
Example: Let f = uwz + uxz + vwz + vxz + yz + uv
• Dividing by kernel (u + v): f = (u + v)(wz + xz) + yz + uv
– fd = (u + v), fq = wz + xz, and fr = yz + uv
• fd and fr cannot be factored any further, but fq can be:
– f = (u + v)(w + x)z + yz + uv
• Further factoring by extracting z:
– f = ((u + v)(w + x) + y)z + uv
• Literal-count: reduced from 16 to 8
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Extraction
For two or more expressions with common divisors: divisors can be
extracted using rectangle covering
• Cube extraction
• Kernel extraction
Cube extraction: Form an auxiliary expression fa as the sum of all
expressions in the logic network
• Obtain a cube-literal incidence matrix for fa
• Tag each cube of each expression with an identifier for that expression
• Find a prime rectangle
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Extraction Example
Example: Let f1 = uwz + uxz + yz + uv and f2 = vz + wyz
• fa = f1 + f2 = uwz + uxz + yz + uv + vz + wyz
• Cube-literal incidence matrix:
• Prime rectangle: ({yz, wyz}, {y,z}) with corresponding cube yz
• Extract yz:
u
v
w
x
y
z
f1 = uwz+uxz+yz+uv
u
v
f1 = uwz+uxz+f3+uv
w
x
f2 = vz+wyz
y
z
f2 = vz+wf3
f3 = yz
• Since literal-count remains at 15 after extraction: not an attractive step in
this case
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Kernel Extraction
Kernel extraction: Define a kernel-cube incidence matrix
• Represent each cube in a kernel with a new variable
• Represent a kernel by a set of such variables
• Denote set of kernels for expression fi by K(fi)
Example: Let f1 = uwz + uxz + yz and f2 = vw + vx + vyz
• From their cube-literal incidence matrices:
– K(f1) = {(w + x), (uw + ux + y)}
– K(f2) = {(w + x + yz)}
• Let aw = w, ax = x, ay = y, auw = uw, aux = ux, ayz = yz
– Thus, K(f1) = {{aw, ax}, {auw, aux, ay}}
– K(f2) = {{aw, ax, ayz}}
• Next, form an auxiliary function fa
– fa = awax + auwauxay + awaxayz
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Kernel-cube Incidence Matrix
Kernel-cube incidence matrix: cubes represent kernels and columns
denote new variables
• Element (i,j) is 1 if jth new variable is used in the ith cube, 0 otherwise
• Prime rectangle corresponds to kernel intersection
• If the rows of such a rectangle correspond to different expressions, the
intersection corresponds to the subexpression that can be extracted
Example: Again, let f1 = uwz + uxz + yz and f2 = vw + vx + vyz
•
•
•
•
Prime rectangle: ({awax, awaxayz}, {aw, ax})
Corresponds to kernel intersection (w + x), which can be extracted
Literal-count: reduces from 15 to 12
f1 and f2 can be factored again to reduce literal-count to 10
u
v
w
x
f3 = w+x
f1 = uzf3+yz
y
z
f2 = vf3+vyz
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Decomposition and Substitution
Decomposition: helps reduce size of a complex expression to more
manageable size implementable with standard logic cells
• Assume algebraic factoring: f = fdfq + fr
• Decomposition represents fd by a: reducing f to afq + fr and a = fd
• Then decomposition can be carried out recursively on the divisor, quotient
and remainder
Example: Let f = xz + yz + wx + wy + vw and consider divisor x + y
f = aw + az + vw v
v
w
w
a=x+y
• Decomposing the
quotient next:
f = ab + vw
a=x+y
b=w+z
x
y
z
f = xz+yz+wx+wy+vw
x
y
a = x+y
f = aw+az+vw
z
v
w
x
y
a = x+y
z
b = w+z
f = ab+vw
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Decomposition and Substitution (Contd.)
End product of decomposition: depends on choice of divisor
• Evaluate all kernels: choose the one that reduces literal-count the most
• Faster alternative: consider level-0 kernels only
Substitution: Process of replacing the divisor by corresponding variable
• Divisor x + y was replaced by variable a: this was substituted into f
• Thus, decomposition and substitution go hand in hand
• If a divisor of f is also a divisor of g: corresponding variable can be
substituted in both f and g
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Technology Mapping
Technology mapping: mapping of circuit components after technologyindependent logic synthesis to logic cells in a cell library
• Possible objectives: minimize area (delay) under delay (area) constraints
Example: Cell library: INV, NAND2, NAND3 with area costs of 1, 2, 3
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w
v
w
x
y
z
x
f
f
y
z
(b) NAND implementation.
(a) Technology-independent
network.
3-input NAND
v
w
v
w
x
y
z
(c) Technology mapping
with area cost 9.
f
x
y
z
f
(d) Technology mapping
with area cost 7.
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Definitions
Network covering: process of replacing subnetworks with logic cells such
that the whole network is covered and desired objective is met
Matching: a cell matches a subnetwork if they are functionally equivalent
Subject graph: logic network converted into a graph with nodes derived
from a set of base functions, e.g., (inverter, two-input NAND)
Pattern graph: implementation of cell library with base functions
(b) NAND2.
(a) INV.
(c) NAND3.
(d) NAND4_1.
(e) NAND4_2.
(f) AOI21.
(g) AOI22.
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Area-delay Costs of Pattern Graphs
Network cover: ensemble of pattern graphs with minimum cost that
collectively matches every node in the subject graph
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Decomposing a Network into Base
Functions
For decomposition: base functions must obviously be functionally complete
and supported by the cell library
• (INV, OR2, AND2)
• (INV, NAND2)
• (INV, NOR2)
Trivial network cover: map each node in the subject graph to the cell that
implements that base function
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Partitioning a Network into Subject
Graphs
Network decomposed into base functions: subsequent technology
mapping cumbersome
• Partition network into a set of connected subject graphs
– Use subnetworks called leaf-DAGs
» Leaf-DAG has no internal fanout
» Thus, fanout points form the boundaries of a partition
• Subject each subject graph to matching and network covering
s2
Example:
u
u
y
u
v
w
s1
f1
u
v
w
x
f3
z
f2
(a) Technology-dependent
network.
y
f1
x
f3
z
s3
f2
(b) Decomposed network and its
subject graphs.
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Obtaining Matches
Obtain all possible ways in which pattern graphs match each node in the
subject graph
• Tree matching: when all pattern graphs are trees (do not have fanout
even at their primary inputs)
Example: Tree matching
w
x
c3
c2
y
c4
c1
z
(a) Subject graph.
f
Node
f
c1
c2
c3
c4
Match
NAND2, NAND3
INV, AOI21
NAND2
NAND2
INV
(b) Matches.
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Obtaining the Network Cover
Choose one match at each node in the subject graph to obtain the network
cover to minimize some cost
• Optimum method: dynamic programming
• Traverse subject graph from primary inputs to output and choose the best
match for each node
Example: Optimum area cost
AOI21
w
x
c3
NAND2
c2
y
c4
c1
f
z
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Obtaining the Network Cover (Contd.)
Example: Optimum delay cost
NAND2
w
x
c3
NAND3
c2
y
c4
c1
f
z
INV
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