PowereLab HKU
A ZVS approach for AC/DC converter with PFC
The Power Electronics Lab., Hong Kong University
N. K. Poon
C. P. Liu
M. H. Pong
Speaker
Bryan M. H. Pong
Power eLab
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1
Some basic concepts
Load


Input rectifiers and capacitor produce Pulsating input current
Harmonic currents are generated
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2
A conventional method
Ipfc

Idc
A boost converter and a DC/DC converter
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3
A popular method among
researchers
Ipfc

Idc
Single stage design which combines the boost and the
DCDC converters
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4
Is single stage design always
better?
Let us take a look
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5
Why two-stage design?
•Advantage
•Losses  Ipfc2 + Idc2
•Fix DCDC input voltage
•Controllable bulk voltage
Ipfc
Idc
•Disadvantage
•Need two controllers
•One more MOSFET
Power eLab
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6
Why single-stage design?
•Advantage
•One controller
•One MOSFET less
Ipfc
•Disadvantage
Idc
•Losses  (Ipfc + Idc)2
•High Idc at low line
•Higher Ipfc
•High current stress
•High voltage stress
Power eLab
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7
Good reasons for two-stage
oTwo-Stage
oSingle Stage
•Advantages
•Advantages
•Losses  Ipfc2 + Idc2
•One controller
•Fix DCDC input voltage
•One MOSFET less
•Controllable bulk voltage
•Disadvantages
•Disadvantages
•Need two controller
•Losses  (Ipfc + Idc)2
•One more MOSFET
•High Idc at low line
•Higher Ipfc
•High current stress
Power eLab
•High voltage stress
HKU
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8
Our new idea
Boost + Asymmetric half-bridge with soft switching
M1
DMpfc > DM2
Mpfc
M2
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9
Zero voltage state - M2
M1 turn off then . .
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10
Zero voltage state - Mpfc
After M2 turn on
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11
Two separate converters
M2 turn on
Mpfc turn on
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12
Zero voltage state – M1
M2 turn off
Mpfc turn on
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13
One cycle on asymmetric
M1 turn on
Mpfc turn on
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14
One cycle on PFC
M1 turn on
Mpfc turn off
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15
It’s great, but . . .
If DMpfc < DM2
DMpfc = DM2
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16
After all –
small Maux added
M1
Mpfc
For all DMpfc
and all DM2
Maux
M2
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17
Final timing arrangement
M2
gate drive
A
M1
gate drive
B
Maux
gate drive
Mpfc
gate drive
VA = VB
VMaux_ds = VA-VB =0
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18
Practical consideration
M1
Mpfc
Maux
M2
Doff
guarantee a path for Laux current
when M2 off at any time
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19
Practical circuit – O/P 12V@10A
250uH
IRF840A
Two diodes are used to
clamp ringing
STD5NM50
12uH
8uH
STPS12NM50
STPS12NM50
Power eLab
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20
Simplified timing circuit
L5991
M2 gate
O/P
Sync
M1 gate
Maux gate
Sync
Mpfc gate
O/P
L4981
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21
How does it look?
Width = 12.6cm
Depth = 6.3cm
Height = 1.9cm
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22
ZVS on M2
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23
ZVS on Mpfc
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24
ZVS on Mpfc & M2
Power eLab
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25
Losses and Efficiency
Power loss vs. Output power at 115V input
Efficiency vs. Input voltage at 12V@10A output
16
12
Efficiency/%
Power loss/W
14
10
8
6
4
2
0
0
24
48
72
96
120
Output power/W
100
98
96
94
92
90
88
86
84
82
80
90
100
115
150
200
230
240
Input voltage/V
Power eLab
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26
Finally . . .
•Simple Boost + Asymmetric Half-bridge
configuration – Good Combination.
•All ZVS behaviors – Very little added cost.
•Two separate converter – Easy to control
•Active diode can be incorporated – <1W no
load power
•Simple PWM controller – simple ASIC
Power eLab
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27