How changes in physical parameters
will affect impedance on a PCB
Embedded / buried capasitance
Multilayer builds and impact on cost,
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Changes in physical parameters will affect impedance as follows:
As Physical Values Change
Dielectric Constant (DK)

Dielectric Thickness ( h )
Line Width
(w)
Line Thickness
(t)


Impedance Will Move




Effect of variables on impedance value.
We can take a simple strip-line configuration, vary one element at a time, and
calculate the resulting value.
BASIC
Two major applications areas, RF/analog and Digital
The major differences between these two areas are the ability of the
PCB involved to tolerate signal losses and the complexity of the PCB.
RF/Analog applications are characterized by the need for low dielectric losses,
low leakage,
a need for a low and uniform
dielectric constant
followed by a low layer count.
Further, since this type of PCB “tends” to be small, cost of the dielectric material
has less effect on overall product cost than on other components.
As a result, using more exotic /expensive materials to meet performance goals is
acceptable. For this class of PCB, choosing a material based on it’s
Dk characteristics and losses usually dominates over other considerations.
Digital applications are characterized by high layer counts, a large numbers of
drilled /plated holes, can have buried / blind and small via holes.
The processing costs associated with registering, laminating/bonding many layers,
drilling and plating ease, usually dominate the choice of materials.
Absolute dielectric constant value of the insulating material is important, but less
important than processing costs and dimensional stability.
As a result, woven glass reinforced materials are nearly always required.
The choice of resin system used with the glass reinforcement is made based on
keeping Z-axis expansion within acceptable limits.
The thicker the PCB, the higher the Tg must be to produce a reliable PCB.
Digital applications are nearly always subjected to pricing pressures, so material
choices must be made to just achieve performance requirements without adding
extra cost.
Typical PCB dielectric (core/prepreg) substrates are constructed from various woven
fiberglass fabrics, strengthened and bound together with epoxy resin.
The numbers next to each diagram identify the glass fabric style based on the fiberglass
thickness, pitch, warp yarn, fill yarn, and the number of glass fiber strands used.
Glass bundle thickness: 106P – 38um
1080P – 63um
2116P – 96um
7268P – 172um
Material Property Comparison between E-Glass and NE-Glass
The primary component of most fiberglass yarns is E-glass, S-glass, or NE-glass.
E-glass or “electronic glass” is the primary glass used in yarns that are used to
construct fiberglass fabrics, and is the least expensive among the three.
S-glass is generally used for non-electrical applications.
NE-glass has improved electrical and mechanical performance over
E-glass and is typical used in the Nelco 4000-13SI and N6000-21SI highperformance laminate product lines.
Skew__
traces that are neither parallel nor intersecting with the glass pattern
- Altera recommends that you pay close attention to the skew/fiber
weave effect for high-speed data rates of 6.375 Gbps and up.
- For identical dielectric materials, wider traces in general show less
susceptibility to fiber weave skew compared to narrow traces.
- If possible, use a dense weave (2116) rather than a sparse weave
such as 106 or 1080 where this effect is predominant.
- For “marginal” cost increase 25% , move to a better laminate
such as Nelco 4000-13 made of NE-glass (lower Er) compared to
the regular E-glass (higher Er).
Skew__
traces that are neither parallel nor intersecting with the glass pattern
- Plan the routing on the board in such a way that the routing ends up
being at an angle rather than orthogonal.
- Make use of zig-zag routing. The trace can be routed so that it
traverses a minimum of 3 times the fiberglass pitch before
reversing the direction of routing.
The drawbacks is the increase in board real estate along with
the difficulty associated with routing at arbitrary routing angles
other than the typical 0°, 45°, and 90 °,
Designers should pay close attention to the layout and the dielectric materials in the PCB design.
At high frequencies, dielectric loss is dominant, and is dependent on the dissipation factor (loss
tangent) for a given dielectric material. The orientation of the trace with respect to the glass
weave determines the amount of skew seen, due to the fiber weave glass pattern.
Prepregs that are more homogeneous , eg 3313 are available, and more will come…..
RELATIVE DIELECTRIC CONSTANT
vs. FREQUENCY FOR VARIOUS LAMINATES
Thickness of coating will influence on impedance
coting is often excluded on RF applications
More S A M P L E s 1/2
Advanced Multilayer build
Material: TU-752
TG 180 ,
Dk: 4.3 / 1GHz __ Dk4.1 / 10GHz
Calculated with Dk 3.8
All copper layers, 1.0oz (35um) Look at line width/space for 50 ohm ss
More S A M P L E s 2/2
Advanced Multilayer build
Material: TU-752
TG 180 ,
Dk: 4.3 / 1GHz __ Dk4.1 / 10GHz
Calculated with Dk 3.8
All copper layers, 0.5oz (17um) Look at line width / space for 50 ohm ss
Crasy ? ..not any longer
Buried Capacitance®
--BC-Product Family
-will improve your Power Distribution System (PDS)
-Noise margin
and improve EMC levels.
A Very Simple Idea
Use the Power
and Ground Planes
to Form Buried
Capacitance (BC) Planes
Within the PCB, and
Remove Most of the
Bypass Capacitors
Remove
BC
Add
Standard Core
BC
Remove
Add
Buried Capacitance ®
Drivers
Decrease Plane Inductances &
Broad Band Impedance
Reduced size or increased functionality
at same size
Lower assembly cost &
higher reliability
- Fewer components= Less solder joints
Buried Capacitance®
Overview
Buried Capacitance®
Technical
High Dk value is positive for the capacitance, will ”not” affect signal- impedance values
Buried Capacitance ®
Conversion
Decrease power plane spacing below 100um
Dramatically improves high frequency capacitance
Closer adjacent power/ground planes reduces plane ∆V due to:
-Increased capacitance at lower frequencies
-Decreased inductance at higher frequencies
Provides additional Z-axis room to increase signal impedances
Representative ZBC Design Example
(Capasitor Elimination)
Based on a 1156 Pin BGA, 3.3V power distribution, 603 Style Bypass Caps
Representative ZBC Design Example
(Plane Resonance Reduction)
W/O BC
100 um std.
Core used.
With BC-24
With ZBC-2000
With BC-12TM
BC Photomicrograph
1 Top
2 Gnd
3 Pwr
4 Sig
5 Sig
6 Pwr
7 Gnd
8 Bot
Capacitance Calculation
Area
Thickness
C = AD/t where
C - is total capacitance
A - is the area per sq. inch of the plane (or split plane)
attached to the active devices
 - is the dielectric constant of the dielectric material
D - is a constant (225)
t - is the thickness of the dielectric material in mils
Example: (10” x 10” PCB)*2 Planes*4.5*225/2
= 101,250 Picofarads, or .1 uF
May not be applicable on small area parts
Electromigration of Copper
Due to Temperature and Humidity
Copper +5 V
Thin Dielectric
Copper 0 V
Copper Ions
BC Has Flat Internal Surfaces to
Distribute the Voltage...and is Tested at
500 VDC
Copper +5 V
Thin Dielectric
Copper 0 V
Full workshop / test report available
High Dk value is positive for the capacitance, will not affect signals and impedance value
Multilayer builds and impact on
cost
$
General information
All data shown in this presentation reflect average price,
adders to illustrate trends as attributes are changed.
Data in all the charts is derived from the following
product conditions:
Regular FR-4 Material
5 mils (0.127mm) lines & spacing.
25 mils (0.635mm) SMT pitch
13 mils (0.3mm) Finished Hole Size
50 holes/sq.in.
SMOBC/HASL
Hierarchy of Cost impact
Cost Breakdown
This chart represents the breakdown of the major cost
components of a PCB..
Layer to Layer Differential
This chart illustrates the cost impact as you increase form one layer count to another.
All other product attributes are assumed to be identical.
A medium complexity product was used for comparison purposes.
Laminate Types
This data reflects the cost impact of different raw materials for a 10 layer board,
and takes into consideration the variation in processing costs and yield implications.
Copper Thickness –Internal
17 um
35 um
70 um
105 um
140 um
175 um
210 um
Data provided is reflective of the copper weight impact on a typical PCB.
Increased material and processing costs are reflected in the data for 2 oz
copper and greater.
Copper Thickness –Outer layers
9 um
12 um
17 um
35 um
70 um
Data is reflective of the starting copper weights prior to plating . Increased
processing costs are reflected in the data for 70um copper,
and yield impacts are reflected in the data for copper weights less than 17um.
Layer Track Width & Spacing –Int./Ext.
127 um
100 um
75 um
This data takes into considerations the variation in processing costs and
yield implications.
There is a slight decrease for lines and spacing greater than 6 mil (150um)
PCB Thickness
1.6mm
1.85mm 2.1mm
2.4mm
2.6mm
2.9mm
3.2mm
Data reflects additional material costs & lower productivity through manufacturing
Minimum Finished Hole Size
FHS > 0.3mm
0.3mm=> FHS > 0.2mm
0.2mm => FHS 0.15mm
This data reflects the minimum drilled hole size in an 1.6mm thick PCB.
PCB thicker than 1.6mm will increase cost.
Hole Aspect Ratio
Since aspect ratio is not linear this data reflects aspect ratios within ___ capabilities..
Controlled Impedance
Cost factors and tolerances are based on a nominal impedance value of 50 Ohms.
Standard working tolerance is +/-5 ohms or 10%, whichever is greater.
Additional costs will be incurred if 100% testing is required.
Surface Finishes
Data reflects the cost impact of surface finishes after soldermask application.
Layer/Technology Impact
Relative impact on the board price
500%
450%
400%
350%
300%
250%
200%
150%
100%
50%
0%
4
6
8
10
12
14
16
18
20
Layers
Type B
Type A
Type A
Type B
Type C
Type C
This chart illustrates the cost impact as you increase form one layer count to
another. A medium complexity product was used for comparison purposes.
Type ‘A’ assumes mass lam up to & including 10 layers. High Tg material is
assumed for greater than 10 layers for all HDI types.
“Simple” material comparison
The End
BASIC
Two major applications areas, RF/analog and Digital
De største forskjellene mellom disse to områdene er evnen kortet har
for å tolerere signal tap og kompleksiteten av kortet
RF / Analog applikasjoner er preget av behovet for lavt
et behov for lav og jevn
fulgt opp av
dielektriske tap,
liten lekkasje,
dielectrisitets
konstant
lavt lag-antall.
Videre, siden denne typen PCB har en tendens til å være små, har kostnaden av
dielektrisk materiale mindre effekt på samlet produkt pris enn andre komponenter.
Som et resultat, bruker av mer eksotiske / kostbare materialer for å møte
resultatmål er akseptabelt. For denne typen av PCB, vil valg av materiale basert
på dets Dk egenskaper og tap-faktor, vanligvis dominere over andre hensyn.
Digitale korts kjennetegn er et høyt lag antall, et høyt antall boret / pletterte
hull, og kan ha begravde / blinde og små via hull.
Prosess- produksjons kostnader forbundet med registrering, laminering /
bonding av mange lag, boring og platings parametre, vil vanligvis dominere
valget av materialer.
Absolutt DK verdi på isolerende materialer er viktig, men mindre viktig enn
prosesserings kostnader og dimensjons-stabilitet. Prispressede produkter.
Som et resultat, blir vevd glassfiberarmert materiale nesten alltid valgt. Valget av
resin som brukes med glass armeringen er gjort basert på å holde Z-akse
ekspansjon innenfor akseptable grenser.
Jo tykkere PCB, jo høyere Tg for å produsere et pålitelig kort. Digital kort er
nesten alltid utsatt for prispress, så materialvalg må gjøres for å ”kun” oppnå
nødvendig krav til ytelse, uten å legge inn en ekstra kostnad.
Typiske PCB dielektrikum (Core / Prepreg) laminater er sammensatt fra ulike vevde
glassfiber matterer og bundet sammen med en epoxy.
Numrene ved siden av hvert bilde unde identifisere glass vev typen basert på glassfiber tykkelse,
avstand, renning, fyll og antallet av glassfiber tråder brukt.
Glass bundle thickness: 106P – 38um
1080P – 63um
2116P – 96um
7268P – 172um
Sammenligning av Material egenskap mellom E-Glass og NE-Glass
Primær- komponenten i de fleste glassfiber garn er E-glass, S-glass, eller NE-glass.
E-glass eller "elektronisk glass" er det primære glasset brukt i veven som benyttes i
glassfiber, og det er den billigste av de tre.
S-glass er generelt benyttet til “ikke elektriske applikasjoner” Vi ser bort fra disse.
NE-glass har forbedret elektrisk og mekanisk ytelse i forhold til E-glass og er
typisk brukt i Nelco 4000-13SI og N6000-21SI. Høy ytelse laminater.
Skew__
ledere som verken er parallelle eller kryssende med glass veven
- Altera anbefaler at en er oppmerksom på skew / fiber ”weave”
effekt for høyhastighets datahastigheter på 6,375 Gbps og oppover.
- For identiske dielektriske materialer, bredere ledere generelt har
mindre mottakelighet for ”fiber weave skew”, sammenlignet med
smale ledere.
- Hvis mulig, bruk en tett veving (2116) heller enn en en mer glissen
vev slik som 106 eller 1080 der denne effekten er dominerende.
- For "marginal" kostnadsøkning, 25%, kan du flytte til en bedre
laminat som Nelco 4000-13 som benytter NE-glass (lavere Er)
sammenlignet med de vanlige E-glass (høyere ER).
Skew__
ledere som verken er parallelle eller kryssende med glass veven
- Planlegg rutingen på kortet på en slik måte at routingen ender opp
vinkel i stedet for ortogonale på veven.
- Benytt deg av sikk-sakk ruting. Ledere kan legges slik at de krysser
minimum 3x glassfiber før du returnerer routingen.
Ulempene er at denne ruting trenger større plass sammen med
annen tradisjonell routing med vinkler på tradisjonell 0°,45°,90 °
Material Cost Comparison