CO2006: Electronics II, Spring 20010
Integrated Circuit Biasing and
Active Loads
張大中
中央大學 通訊工程系
dcchang@ce.ncu.edu.tw
中央大學 通訊系 張大中
Electronics II, 2010
1
Two Transistor Current Source
 The two-transistor current source is also called a current mirror, which consists of two
matched (or identical) transistors, Q1 and Q2, operating at the same temperature.
I REF  I C1  I B1  I B 2  I C1  2 I B1

2
 I C 2  2 I B 2  I C 2 1  
 
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
2
I O  I C 2  I REF 1  
 
I REF
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V   VBE  V 

R1
2
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3
Output Resistance with Early Effect
 Taking the Early effect into account
IO
I REF
1
1  VCE 2 / VA


1  2 /  1  VCE 1 / VA
VCE 2  VI  VBEo  V 
For finite Early voltage, a change in the VI
dc bias condition in the load circuit affects
the collector-emitter voltage of Q2.
ro
dI O
I
1
1
 REF  
dVCE 2 1  2 /  VA 1  VBE / VA

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IO 1

(VBE  VA )
VA rO
4
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5
Mismatched Transistors
 In practice, transistor Q1 and Q2 may not be exactly identical.
I REF  I C1  I S 1eVBE /VT
I O  I C 2  I S 2eVBE /VT
If Q1 and Q2 are not identical, then I S1  I S 2 .
 Relationship between the bias and reference currents
I 
IO  I REF  S 2 
 I S1 
 I S is a strong function of temperature. Thus Q1 and Q2 must be close to one
another on the semiconductor for the similar operation situation (including temperature).
 By using different sizes of transistors, we can design the circuit such that
I O  I REF .
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6
Basic Three Transistor Current Source
Assume that all transistor are identical.
I REF  I C1  I B 3
I B3 
IE3
2I B2
2 IO


1   3 1   3  2 (1   3 )
I C1  I C 2  I O
I REF
ro 2


2 IC 2
2
 IC 2 
 I C 2 1 

 2 (1  3 )

(
1


)
2
3 



2
I O  I REF 1 


(
1


)
2
3 

I REF
V   VBE 3  VBE  V 

R1


V  2VBE  V
R1
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
• The approximation of I O  I REF is better.
• The change in load current with a change in  is much
smaller.
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7
Cascode Current Source
 Current-source circuits can be designed such that the output resistance is much greater
than that of the two-transistor circuit.
 For a constant reference current, the base voltages of Q2 and Q4 are constant, which
implies these terminals are at signal ground.
Vbe4   I x ( ro 2 // r 4 )
Assume that all transistor are identical.
 V  I x ( ro 2 // r 4 ) 

I x  g m 4Vbe4   x
ro 4


 Vx  I x ( ro 2 // r 4 ) 

  g m 4 I x ( ro 2 // r 4 )  
ro 4


V
Ro  x  ro 4 (1   )  r 4
Ix
 ro4
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8
Resistance Analysis of the Cascode Current Source
ib
ib
io 4
gm 4Vbe4  gm 4 ( ro 2 // r 4 )ib
io 4  [1  gm 4 ( ro 2 // r 4 )]ib
Ro  ( ro 2 // r 4 )  ro 4 [1  g m 4 ( ro 2 // r 4 )]
 r 4  ro 4 (1  g m 4 r 4 )
 r 4  ro 4 (1   )
 ro 4
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9
Wilson Current Source
I REF  I C1  I B 3  I C 2  I B 3
Assume that all transistor are identical.

2
I E 3  I C 2  2 I B 2  I C 2 1  
 
1 

2
1
I C 2  I E 3 1   

IC 3

   1 2 / 
ro 3 / 2
1 

IC 3
2
1 
IC 3
I REF 
IC 3 
2

1
I O  I REF 
2
1
 (2   )
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10
Widlar Current Source
I REF  I C1  I S eVBE 1 /VT (   1)
IO  IC 2  I S e
VBE 2 / VT
Assume that all transistor are identical.
 I REF 

VBE1  VT ln 
 IS 
 IO 
VBE 2  VT ln  
 IS 
I 
VBE1  VBE 2  VT ln  REF 
 IO 
 I E 2 RE  I O RE
 I REF 

I O RE  VT ln 
 IO 
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VBE1  VBE 2  IO  I REF
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Output Resistance
1
Ro1  r 1 //
// ro1 // R1
g m1
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(For typical parameters, it is small.)
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Output Resistance
V 2   I x ( RE // r 2 )
Vx  I x ro 2  gm 2 ro 2V 2  I x( RE // r 2 )
Vx
 Ro  ro 2 1  ( RE // r 2 )( g m 2  1 / ro 2 )
Ix
 ro 2 [1  g m 2 ( RE // r 2 )]
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Multitransistor Current Mirrors
I O1  I O 2  ...  I ON 
I REF
1 N
1

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Multioutput Transistor Current Source
I1  I 2  I 3  I REF
IO  3I REF
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Generalized Current Mirrors
Assume that all transistor are identical and
the base current effects are neglected.
I REF
V   VEB (QR1 )  VBE (QR 2 )  V 

R1
I O1  I REF
I O 2  2 I REF
I O 3  I REF
I O 4  3I REF
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Two Transistor MOSFET Current Source
I REF  K n1 (VGS  VTN 1 )2
VGS  VTN 1 
I REF
Kn1
I O  Kn 2 (VGS  VTN 2 )2
 I

 Kn 2  REF  VTN 1  VTN 2 
 K n1

2
If M1 and M2 are identical
transistors, then I O  I REF .
The output current can be
controlled by aspect ratios,
IO 
Kn 2
(W / L) 2
 I REF 
 I REF
K n1
(W / L)1
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Output Resistance
 Taking into account the finite output resistance of transistors,
I REF  Kn1 (VGS  VTN 1 )2 (1  1VDS1 )
I O  Kn 2 (VGS  VTN 2 )2 (1  2VDS 2 )
Assume that all physical parameters are identical for both devices.
IO
I REF

(W / L) 2 (1  VDS 2 )

(W / L)1 (1  VDS1 )
Let (W / L)2  (W / L)1 .
1
dI O
1

 I REF 
RO dVDS 2
ro
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ro
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21
Reference Current
 The M3 transistor is used as a resistor.
K n1 (VGS1  VTN 1 )2  K n 3 (VGS 3  VTN 3 )2

(W / L)3
(W / L)3
VGS1 
 VGS 3  1 
(W / L)1
(W / L)1


  VTN


V   VGS1  VGS 3  V 
k
1 k
 (V   V  ) 
VTN
1 k
1 k
 VGS 2
VGS1 
k
(W / L)3
(W / L)1
W   1

IO     nCox (VGS 2  VTN )2
 L 2  2

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Cascode Current Mirror
 The output resistance is designed to be much greater
than that of the two-transistor circuit.
I x  gmVgs4 
Vx  ( Vgs4 )
ro 4
Vgs 4   I x ro 2
Ix 
ro 2
V
I x  g m ro 2 I x  x
ro 4
ro 4
Ro 
Vx
 ro 4  ro 2 (1  g m ro 4 )
Ix
 ro 4  g m ro 2 ro 4
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25
Wilson Current Mirror
 For modified MOSFET Wilson current source circuit, the drain-to-source voltages of M1,
M2, and M4 are held constant.
 The primary advantage of these circuits is the increase in output resistance, which
further stabilizes the load current.
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Bias-Independent Current Source
 PMOS devices are matched, the
current I D1 and I D 2 are equal.
kn  W 
2
  (VGS1  VTN )
2  L 1
kn  W 
 I D 2    (VGS 2  VTN ) 2
2  L 2
I D1 
(W / L)1
 (VGS1  VTN )  VGS 2  VTN
(W / L)2
Always
Saturation
VGS 2  VGS1  I D 2 R  VGS1  I D1R
 I D1  K n1 (VGS1  VTN ) 2
 VGS1  VTN 
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I D1
K n1
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Bias-Independent Current Source
(W / L)1
 (VGS1  VTN )  VGS 2  VTN
(W / L)2
(W / L)1
I
 D1  VGS1  VTN  I D1R
(W / L) 2
K n1

R
1
K n1 I D1
I D1
 I D1 R
K n1

(W / L)1
1 

(W / L) 2


 (For a given current I D1 , one

 can find the value of R.)
The currents I D1 and I D 2 are independent of the supplied voltages as
long as M2 and M3 are biased in the saturation region.
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JFET Current Sources
 The device remains biased in the saturation region.
vDS  vDS (sat )  vGS  VP | VP |
(VP is negative)
In the saturation region, the current is
2
 v 
iD  I DSS 1  GS  (1  vDS )  I DSS (1  vDS )
VP 

1
di
 D  I DSS
ro dvDS
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Cascode JFET Current Source
 Increase the output resistance of a JFET current source
Assuming Q1 and Q2 are identical,
2
 v 
iD  I DSS (1  vDS1 )  I DSS 1  GS 2  (1  vDS 2 )
VP 

vGS 2  vDS1, vDS 2  VDS  vDS1
For a given VDS , vDS1 (and then iD ) can be determined by
2
 vDS1 
 [1   (VDS  vDS1 )]
(1  vDS1 )  1 
VP 

 Output Resistance
I x  gmVgs2  [Vx  ( Vgs2 )] / ro 2
 gm (  I x ro1 )  [Vx  ( Vgs2 )] / ro 2
Ro 
Vx
 ro 2  ro1  g m ro1ro 2
Ix
 ro 2  ro1 (1  g m ro 2 )
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DC Analysis of BJT Active Load Circuits
 Q2 is referred to as the active load device for driver transistor Q0.
 V 
I C 0  I S 0 [eVI /VT ]1  CE 0 
 VAN 
 V 
I C 2  I S 2 [eVEB 2 /VT ]1  EC 2 
VAP 

 V 
I REF  I C1  I S1[eVEB1 /VT ]1  EC1 
 VAP 
Assuming Q1 and Q2 are identical,
I S1  I S 2 and VEC1  VEB1  VEB2 .
VO  VCE 0
V V
 AN AP
VAN  VAP
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 I S 0eVI /VT 
VAN

1


(
V
 VEB2 )


I REF  VAN  VAP

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Voltage Gain of BJT Active Load Circuits
 Voltage Transfer Function and Load Curve
VCE 0 (sat )  VO  V   VEC 2 (sat )
 Voltage Gain
 VANVAP  I S 0  1
dVO


Av 
 
dVI
 VAN  VAP  I REF  VT
 VI /VT
e

I REF  I S 0eVI /VT
 VANVAP  1
dVO

Av 
 
dVI
 VAN  VAP  VT
 (1 / VT )

1
1

VAN VAP
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


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DC Analysis of MOSFET Active Load Circuit
I REF  K p1 (VSG  | VTP1 |)2 (1  1VSD1 )
I 2  K p 2 (VSG  | VTP 2 |)2 (1  2VSD2 )
Assuming M1 and M2 are identical,
1  2   p , VTP1  VTP 2  VTP , and K p1  K p 2  K p .
VSD1  VSG , VO  V   VSD 2
(1   pVSG )
I REF (1   pVSD1 )


I2
(1   pVSD 2 ) (1   p (V   VO ))

VO 
I REF
K n (VI  VTN )2 (1  nVO )
[1   p (V   VSG )]
n   p
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Kn (VI  VTN )2

I REF (n   p )
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Voltage Gain of MOSFET Active Load Circuits
 Voltage Transfer Function and Load Curve
 Voltage Gain
Av 
dVO  2 Kn (VI  VTN )

dVI
I REF (n   p )
gm  2 Kn (VI  VTN )
ron  1 / n I REF
Av 
 gm
 1

1
  
r

r
on
op


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rop  1 /  p I REF
  g m ( ron // rop )
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Small-Signal Analysis of BJT Active Load Circuit
 In the Q1 portion of the equivalent circuit, there are no
independent AC sources to excite any current or
voltages.
V 1  V 2  0
Ro  ro 2
Ro  ro 2
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Small-Signal Voltage Gain
Av 
Vo
  g m ( ro // RL // ro 2 )
Vi
g m  I Co / VT
 gm
 gm


1 1
1  g 0  g L  go 2
 
 
 ro RL ro 2 
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go  I Co / VAN
go 2  I Co / VAP
g L  1 / RL
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Small-Signal Analysis of MOSFET Active Load circuit
 There is no AC excitation, the signal voltage Vsg1 and Vsg 2
are zero.
Ro  ro 2
Ro  ro 2
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Small-Signal Voltage Gain
Av 

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Vo
  g m ( ro // RL // ro 2 )
Vi
 gm
g 0  g L  go 2
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Advanced MOSFET Active Load
gmVgs1 
Vo

Ro3
 Vgs2
 gmVgs2 
ro1
Vo  ( Vgs2 )
ro 2
Vo  ( Vgs2 )
 gmVgs2  0
ro 2
Vo
 gm2
 gm2
Av  

gm
1
1
1
Vi


Ro 3 ro1ro 2 ro 3ro 4 ro1ro 2
Ro 3  ro 3  ro 4 (1  gm ro 3 )
(See Cascode Current
Mirror, p.24)
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