Architecture and Applications
of DSP
Edutech Systems
About Edutech Systems
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Interactive Learning Resource
Development Company
Offers Learning Resources for
Embedded and DSP learning
Firmware development
Hardware consultancy services
Training
Learning Resources
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Tutors, CBT, WBT etc
Simulators
Compilers
Programmers, Debuggers, Emulators
CPU boards
Interfacing Modules
Laboratory Workbooks
What is Embedded System?
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“An embedded system is an application
that contains at least one
programmable computer typically in the
form of a microcontroller, a
microprocessor or digital signal
processor chip
Examples of Embedded Systems
Examples of embedded systems are
 Controller in washing machine,
 Controller in compact disk player,
 The navigation system in an aircraft,
 The controller of a robot arm.
How ES are characterized?
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ESs are a special class of electronic systems
that can be briefly characterized by following
terms:
Single-functioned
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Tightly-constrained
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Executes a single program, repeatedly
Low cost, low power, small, fast, etc.
Reactive and real-time
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Continually reacts to changes in the system’s environment
Must compute certain results in real-time without delay
A “short list” of Embedded Systems
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Automotive electronics
Aircraft electronics
Railways
Telecommunication
Medical systems
Military applications
Authentication circuits
Consumer electronics
Fabrication equipment
Smart buildings
Robotics
Embedded System Structure
Digital Signal Processing
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Digital Signal Processing (DSP) is concerned with the
digital representation of signals
Digital signal processing is the mathematical
manipulation of an information signal to modify or
improve it in some way.
Digital signal processing and analog signal
processing are subfields of signal processing.
The goal of DSP is usually to measure, filter and/or
compress continuous real-world analog signals.
Digital Signal Processor
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DSP algorithms have long been run on standard
computers, on specialized processors called digital
signal processor which is a specialized
microprocessor with an architecture optimized for the
operational needs of digital signal processing.
Analog
Signal
ADC
Digital
Signal
Processing
DAC
Analog
Signal
Applications of Digital Signal
Processing
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Audio and speech signal processing
Sonar and radar signal processing
Sensor array processing
Spectral estimation
Statistical signal processing
Digital image processing
Signal processing for communications
Control of systems
Biomedical signal processing
Speech codec in cell phone
Overview of Signal Processing
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The goal of DSP is usually to measure, filter and/or
compress continuous real-world analog signals.
Analog signals typically vary continuously with time;
however, in order to process analog signals with a
CPU, we must first acquire digital samples to be
processed. When samples of a continuous input
signal are captured as digital data, a waveform is
considered a discrete time signal.
Overview of Signal Processing
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The time between the samples is known as the sampling
period. The sampling period is usually constant for a
particular signal being sampled. The reciprocal of the
sampling period is known as the sampling frequency fs.
The sampling frequency must be at least twice the
bandwidth of the signal being processed according to the
Nyquist sampling theorem.
Examples: Traditional telephony signals: 4 KHz, fs=8 KHz,
samples every 125 ms
Wideband telephony signals: 8 KHz, fs=16 KHz, samples
every 62.5 ms
CD audio signals: 22 KHz, fs=44 KHz, samples every 27
ms
DSP Building Blocks
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Digital signal processing algorithms are typically built
up from three basic functions: Add, Multiply, and
Delay.
The first function is an adder; it adds samples of two
or more discrete time signals. Samples are added for
all values of n, as shown in figure
DSP Building Blocks (Contd.)
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The second function is the multiplier; the multiply
block scales all samples in the discrete time signal by
the same scaling factor, as shown in figure.
DSP Building Blocks (Contd.)
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The third key building block for a DSP algorithm is a
delay function. The delay function shifts the samples
to the right.
DSP Building Blocks (Contd.)
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Feed forward System
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Feedback System
Data Acquisition
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The A/D converts the sample analog signal and
provides an integer value representing the signal
sampled. There are a wide range of A/D converters
available with varying resolutions.
The resolution is defined by the number of bits used
to represent the full range of the sampled signal;
common resolutions are 8, 10, 11, 12, 14, 16, and 24
bits.
For audio sample acquisition component known as
codec is attached via the HD audio interface.
The RealTek Codec is such a device that can be
used to convert between the analog audio domain
and the digital domain of the processor.
DSP Algorithm Implementation
DSP Algorithm
Fixed Point
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Floating Point
For example, a 16-bit integer can represent a maximum
range of 65,536. Floating-point implementations, on the
other hand, can represent a much larger dynamic range,
as floating-point representations are designed to
represent both very small and very large numbers.
Under certain standardization a 32-bit floating-point
(single precision) positive number has a range of 2-149 to
3.403 X 1038.
Fixed Point Vs Floating Point
Selection
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Different numeric formats
Cost Vs ease of use
Floating point computational accuracy (e.g. Radar for
navigational aid)
Data set decision
Mathematical flexibility
COMPARISION BETWEEN DSPS &
MICROCONTROLLER
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Microcontrollers and Digital Signal Processors (DSPs) are the
main engines of the deeply embedded development world.
A MICROCONTROLLER is a highly integrated chip which includes, on
one chip, all or most of the parts needed for a controller, is used to
control some process or aspect of the environment. The
microcontroller could be called a "one-chip solution". DSPs are a highspeed single chip microprocessor or microcomputer designed to
perform computer intensive digital signal processing tasks.
Microcontrollers are primarily used in control-oriented applications that
are interrupt-driven, sensing and controlling external events.
DSPs, meanwhile, are traditionally found in systems that require the
precision processing of analog signals.
Microcontrollers are inexpensive, small, and flexible. DSP is larger,
more expensive, and more specialized.
Introduction to DSP C6748
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375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
C674x Instruction Set Features
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Superset of the C67x+ and C64x+ ISAs
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Up to 3648 MIPS and 2746 MFLOPS
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Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
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8-Bit Overflow Protection
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Bit-Field Extract, Set, Clear
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Normalization, Saturation, Bit-Counting
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Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
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32KB of L1P Program RAM/Cache
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32KB of L1D Data RAM/Cache
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256KB of L2 Unified Mapped RAM/Cache
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Flexible RAM/Cache Partition (L1 and L2)
Features
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Enhanced Direct Memory Access Controller 3 (EDMA3):
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2 Channel Controllers
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3 Transfer Controllers
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64 Independent DMA Channels
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16 Quick DMA Channels
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Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core
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Load-Store Architecture with Nonaligned Support
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64 General-Purpose Registers (32-Bit)
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Six ALU (32- and 40-Bit) Functional Units
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Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
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Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
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Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
Features
Two Multiply Functional Units:
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Mixed-Precision IEEE Floating-Point Multiply Supported up to:
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2 SP x SP → SP Per Clock
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2 SP x SP → DP Every Two Clocks
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2 SP x DP → DP Every Three Clocks
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2 DP x DP → DP Every Four Clocks
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Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
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Instruction Packing Reduces Code Size
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All Instructions Conditional
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Hardware Support for Modulo Loop Operation
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Protected Mode Operation
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Exceptions Support for Error Detection and Program Redirection
Software Support
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TI DSPBIOS
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Chip Support Library and DSP Library
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Features
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128KB of RAM Shared Memory
1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
Two External Memory Interfaces:
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EMIFA
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NOR (8- or 16-Bit-Wide Data)
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NAND (8- or 16-Bit-Wide Data)
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16-Bit SDRAM with 128-MB Address Space
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DDR2/Mobile DDR Memory Controller with one of the following:
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16-Bit DDR2 SDRAM with 256-MB Address Space
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16-Bit mDDR SDRAM with 256-MB Address Space
Three Configurable 16550-Type UART Modules:
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With Modem Control Signals
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16-Byte FIFO
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16x or 13x Oversampling Option
LCD Controller
Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O
(SDIO) Interfaces
Features
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Two Master and Slave Inter-Integrated Circuits
(I2C Bus)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High
Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
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Two Independent Programmable Real-Time Unit (PRU) Cores
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32-Bit Load-Store RISC Architecture
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4KB of Instruction RAM Per Core
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512 Bytes of Data RAM Per Core
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PRUSS can be Disabled via Software to Save Power
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Register 30 of Each PRU is Exported From the Subsystem in Addition to the
Normal R31 Output of the PRU Cores.
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Standard Power-Management Mechanism
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Clock Gating
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Entire Subsystem Under a Single PSC Clock Gating Domain
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Dedicated Interrupt Controller
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Dedicated Switched Central Resource
Features
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USB 1.1 OHCI (Host) with Integrated PHY (USB1)
USB 2.0 OTG Port with Integrated PHY (USB0)
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USB 2.0 High- and Full-Speed Client
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USB 2.0 High-, Full-, and Low-Speed Host
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End Point 0 (Control)
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End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX
One Multichannel Audio Serial Port (McASP):
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Two Clock Zones and 16 Serial Data Pins
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Supports TDM, I2S, and Similar Formats
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DIT-Capable
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FIFO Buffers for Transmit and Receive
Two Multichannel Buffered Serial Ports (McBSPs):
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Supports TDM, I2S, and Similar Formats
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AC97 Audio Codec Interface
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Telecom Interfaces (ST-Bus, H100)
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128-Channel TDM
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FIFO Buffers for Transmit and Receive
Features
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10/100 Mbps Ethernet MAC (EMAC):
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IEEE 802.3 Compliant
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MII Media-Independent Interface
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RMII Reduced Media-Independent Interface
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Management Data I/O (MDIO) Module
Video Port Interface (VPIF):
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Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture
Channels
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Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
Universal Parallel Port (uPP):
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High-Speed Parallel Interface to FPGAs and Data Converters
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Data Width on Both Channels is 8- to 16-Bit Inclusive
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Single-Data Rate or Dual-Data Rate Transfers
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Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
Serial ATA (SATA) Controller:
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Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
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Supports All SATA Power-Management Features
Features
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Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit GeneralPurpose Timers)
Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
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Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
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6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric
Outputs
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Dead-Band Generation
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PWM Chopping by High-Frequency Carrier
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Trip Zone Input
Packages:
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361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
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361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
Commercial, Extended, or Industrial Temperature
DSP C6748 Block Diagram
Introduction to EPB_C6748
EPB_C6748 Features
Mechanical Parameters
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Size: 160mm x 136mm
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Input Voltage - 5V DC
Processor
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TMS320C6748 – Fixed/ Floating Point Digital Signal Processor
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DSP with up to 456 MHz performance.
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On board 14 Pin (2x7 Pin) JTAG emulation connector
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Boot mode selection switch
Memory
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On board 256 MB Flash memory
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On board 128 MB DDR2 RAM memory
EPB_C6748 Features
Data Transfer Interfaces
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On board DB9 connector for UART-1 interface
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On board 3 pin header for UART-2 interface
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On board USB TYPE B Connector for UART-2 interface for Debug Console
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LED indication for USB connection for Debug Console
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On board Reset Switch with LED indication
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On board USB Type A Connector for USB host interface
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On board micro USB Type A Connector for USB OTG interface
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On board RJ45 connector for 10/100 Ethernet interface
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On board I2C based Temperature sensor
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On board I2C based RTC interface with battery backup
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On board SPI based micro SD card interface
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On board SATA connector
EPB_C6748 Features
Input/Output Interfaces and other Facilities
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On board Power-On LED indication
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On board 4 User LED at GPIO Pin as GPIO Test point
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On board 5 user push buttons for various applications
Special functionality
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Boot mode selection switch
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On board Video in and Video out port available
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On board VGA out connector
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On board Graphics LCD interface connector
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On board audio jack and speaker(Mic in) interface and audio coded for speaker out
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On board CMOS sensor connector to interface CMOS camera
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On board Temperature sensor with interrupt out facility
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On board LED to indicate high voltage input
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On board excessive voltage protection circuit with LED indication
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Various test points for various signals
Hands-On Session with C6748
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Creating a New Project
Introduction to command file
Introduction to Gel File
Basic DSP based Examples
Filter Examples
Image Processing
Video Processing
Thank You..!
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Thank you..!
Thanks
EDUTECH SYSTEMS
TEL: 0265-2438317
Mail: info@edutechonline.com
Site: www.edutechonline.com
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