EXTERNAL INTERRUPT
REQUEST MODULE
(IRQ)
External Interrupt Module MTT48 13 - 1
Module Objective
By the end of this module, you should be able to:
•Enable/disable IRQ interrupts
•Configure the trigger sensitivity
•Acknowledge the interrupts
•Configure port external interrupts
External Interrupt Module MTT48 13 - 3
EXTERNAL INTERRUPT (IRQ)
MODULE
Clock
Generation
Module
(CGM)
System
Integration
Module
(SIM)
LVI
IRQ
COP
BREAK
RESET
68HC08
CPU
Timer
Interface
Module
(TIM)
Direct
Memory
Access
Module
(DMA)
Internal Bus (IBUS)
Serial
Communications
Interface
(SCI)
Serial
Peripheral
Interface
(SPI)
Random
Access
Memory
(RAM)
Electronically
Programmable
Memory
(EPROM)
Monitor
ROM
Supports external interrupt functions
Two dedicated external interrupt pins
• IRQ1/Vpp and IRQ2
• Individually programmable
• Separate interrupt masks
• IRQ2 Interrupt Disable
Configurable Port as external interrupts
• Allows additional external interrupts
External Interrupt Module MTT48 13 - 4
Global Interrupt Mask
READ:
CCR
V
1
1
H
I
N
C
Z
x
1
1
x
1
x
x
x
WRITE:
RESET:
Code Condition Register (CCR)
• Global CPU interrupt disable mask
1 = All CPU interrupts are disabled
• SWI interrupt is non-maskable
0 = CPU interrupts are processed
External Interrupt Module MTT48 13 - 5
FROM RESET
YES
IRQ Interrupt Flowchart
I BIT SET?
NO
INTERRUPT?
YES
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
External Interrupt Module MTT48 13 - 6
IRQ1 Block Diagram
ACK1
VDD
CLR
D Q
IRQ1/Vpp
SYNCHRONIZER
CK
IRQ1
LATCH
IRQ1
INTERRUPT
REQUEST
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
External Interrupt Module MTT48 13 - 7
IRQ1
Interrupt request is latched on falling edge
Trigger may be edge sensitive only or level and edge sensitive
Maskable through IMASK1 bit
CPU automatically clears request during interrupt processing
• Software may optionally clear the request
Vector address is $FFFA and $FFFB (68HC708XL36)
External Interrupt Module MTT48 13 - 8
IRQ1 Control
READ:
0
PIN2
ISCR
WRITE:
RESET:
0
IMASK2 MODE2 IRQ2DIS
ACK2
0
0
IMASK1 MODE1
ACK1
0
0
0
0
0
0
IRQ Status and Control Register (ISCR)
• IRQ1 edge/level select (MODE1)
– Selects trigger sensitivity of the IRQ1 pin
1 = Interrupt requests on falling edges or low levels
0 = Interrupt requests on falling edges only
• IRQ1 Interrupt Mask (IMASK1)
1 = IRQ1 Interrupts requests disabled
0 = IRQ1 Interrupts requests enabled
• IRQ1 Interrupt request acknowledge (ACK1): write-only
– Used to Clear the IRQ1 request
Writing logic 1 clears the IRQ latch
– Always reads as logic zero.
External Interrupt Module MTT48 13 - 9
IRQ2 Block Diagram
CONFIGURABLE
PORT PINS
ACK2
V
DD
D
IRQ2DIS
CLR
Q
SYNCHRONIZER
CK
IRQ2/KEYBOARD
INTERRUPT LATCH
IRQ2
IMASK2
IRQ2/
KEYBOARD
INTERRUPT
REQUEST
PIN2
MODE2
External Interrupt Module MTT48 13 - 10
IRQ2
Interrupt request is latched on falling edge
Trigger may be edge sensitive only or level and edge sensitive
Maskable through the IMASK2 bit
CPU automatically clears request during interrupt processing
• Software may optionally clear the request
Vector address is $FFE0 and $FFE1 (68HC708XL36)
External Interrupt Module MTT48 13 - 11
IRQ2 Control
READ:
ISCR
PIN2
WRITE:
RESET:
0
ACK2
0
0
IMASK2 MODE2 IRQ2DIS
0
IMASK1 MODE1
ACK1
0
0
0
0
0
0
IRQ Status and Control Register (ISCR)
•
IRQ2/Keyboard Interrupt edge/level select (MODE2)
– Selects trigger sensitivity of the IRQ2 and Keyboard Interrupt Pins
1 = Interrupt on falling edges or low levels
0 = Interrupt on falling edges only
•
IRQ2/Keyboard Interrupt Mask (IMASK2)
1 = IRQ2 and Keyboard Interrupts disabled
0 = IRQ2 and Keyboard Interrupts enabled
•
–Reflects the current level of the IRQ2 pin
–Can be used to distinguish between Port
interrupt and an actual IRQ2 interrupt
IRQ2/Keyboard Interrupt request acknowledge (ACK2)
– Used to Clear the IRQ2/Keyboard requests
Writing logic 1 acknowledges the request
– ACK2 always reads as logic zero
•
•IRQ2 Pin state (PIN2)
1 = IRQ2 pin at logic one
0 = IRQ2 pin at logic zero
IRQ2 Pin Interrupt Latch Disable (IRQ2DIS)
– Prevents the IRQ2 pin from latching interrupt requests into the IRQ2/Keyboard interrupt latch
1 = IRQ2 pin interrupt requests not latched
0 = IRQ2 pin interrupt requests latched
External Interrupt Module MTT48 13 - 12
Configurable Port Interrupts
Block Diagram
PTD0/KBD0
TO PTD0
PULL-UP
ENABLE
.
.
KB0IE
.
ACK2
V
DD
PTD7/KBD7
D
TO PTD7
PULL-UP
ENABLE
IRQ2DIS
CLR
Q
SYNCHRONIZER
CK
KB7IE
IRQ2/KEYBOARD
INTERRUPT LATCH
IRQ2
IMASK2
IRQ2/
KEYBOARD
INTERRUPT
REQUEST
PIN2
MODE2
External Interrupt Module MTT48 13 - 13
Keyboard Interrupt Pins
Port D pins can be enable as port interrupts
• Interrupt requests are latched into the IRQ2/Keyboard Interrupt Latch
• Interrupt request is latched on falling edge
• Trigger may be edge sensitive only or level and edge sensitive
• Generate an IRQ2 interrupt request
• Vector address is $FFE0 and $FFE1 (68HC708XL36)
External Interrupt Module MTT48 13 - 14
Keyboard Interrupt Control
READ:
KBICR
KB7IE
KB6IE
KB5IE
KB4IE
KB3IE
KB2IE
KB1IE
KB0IE
0
0
0
0
0
0
0
0
WRITE:
RESET:
Keyboard Interrupt Control Register (KBICR)
• Keyboard Interrupt Enable bits (KB7IE - KB0IE)
– Enables corresponding keyboard interrupt pin to latch interrupt request
– Port pin data direction automatically changed to input
1 = Corresponding Keyboard interrupt pin enabled and pull-up device on
0 = Corresponding Keyboard interrupt pin disabled and pull-up device off
External Interrupt Module MTT48 13 - 15
Summary
READ:
CCR
V
1
1
H
I
N
C
Z
x
1
1
x
1
x
x
x
WRITE:
RESET:
READ:
ISCR
PIN2
WRITE:
RESET:
0
IMASK2 MODE2 IRQ2DIS
ACK2
0
0
0
IMASK1 MODE1
ACK1
0
0
0
0
0
0
READ:
KBICR
KB7IE
KB6IE
KB5IE
KB4IE
KB3IE
KB2IE
KB1IE
KB0IE
0
0
0
0
0
0
0
0
WRITE:
RESET:
External Interrupt Module MTT48 13 - 16