DMA CONTROLLER
WHOLE WORKING
8237 DMA Controller
8237 DMA Controller Summary
• Direct Memory Access means that the
microprocessor is not involved in the transfer
of data
• The 8237 takes control of the address and
data bus and facilitates the transfer of data
between an I/O device and memory or between
memory and memory
• Realize that the only time one really needs the
CPU is in decoding and executing instructions
8237: The Devil’s in the Details!
• The DMA process starts with a request (DREQ)
from a peripheral
• The 8237 in turn requests the CPU (HRQ) to
kindly get out of the way
• The CPU responds with hold acknowledge (HLDA)
and relinquishes control of the data bus and the
address bus
• The 8237 in turn acknowledges to the peripheral
that the DMA will shortly be underway
8237 Pin Functions . . .
• D0/A8 - D7/A15 These are multiplexed lines that
supply data as well as the MSB of the 16-bit
address. The rest of the address bits are provided
by the processor into a page register
• A0 - A7 During DMA these lines provide the LSB of
the 16-bit address. During configuration of 8237,
A0 -A3 are used by the CPU to address the internal
registers of the 8237 and A4-A7 are disabled
• ADSTB This output from the 8237 is used to
demultiplex the MSB of the address from the data.
ADSTB goes high to indicate valid address on the
multiplexed data/address lines D0/A8 - D7/A15
Inside the 8237 . . .
• There are 4 DMA channels. For each channel there
are two 16-bit address registers. One holds the
base address (initial address). As the DMA cycle
gets underway, the address changes to point to the
current location. This is held in the current
address register.
• The count registers hold number of bytes of data
that must be transferred. All four channels can
transfer data between I/O and memory
• For memory to memory transfers channels 0 and 1
are used and channel 0 is always the source and
channel 1 is the destination.
Many modes . . . many moods!
• There are four modes of DMA transfer. The single
mode transfers one byte of data
• In block transfer, the number of bytes programmed
in the count register is transferred unless EOP
occurs prematurely
• Demand transfer is similar to block transfer with
the additional feature that the peripheral can stop
DMA by deactivating DREQ
• Cascading is not a mode per se but applies to a
situation, as in the PC, where the slave's HRQ is
connected to the DREQ of the master and the
slave's HLDA is connected to the DACK of the
master. That particular channel of the master is
then programmed to be in the cascade mode
8237 USER ACCESSIBLE REGISTERS
ADDRESS [CS + ?]
REGISTER
R/W
0
1
2-7
CH 0 ADDRESS
CH 0 COUNT
AS ABOVE FOR CH 1 - CH 3
R/W
R/W
8
8
COMMAND
STATUS
W
R
9
A
B
C
REQUEST
MASK (SINGLE)
MODE
BYTE POINTER
W
W
W
W
D
D
TEMPORARY
MASTER CLEAR
R
W
E
F
CLEAR MASKS
MASK (ALL)
W
W
How about an example . . . please?
An 8237 is decoded in I//O space so that -CS is
selected if the address is 350H. What are the
addresses of the mode ,command , channel 2
address, channel 2 count, and page registers?
Solution to the example . . .
From the chart of 8237 user accessible registers,
we see that:
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CH2 address
354H
CH2 count
355H
Command
358H
Mode Register
35B
Page register not known. It is not an 8237
register! More info needed
•
Note that this assumes that A0-A3 from the CPU are connected to
A0-A3 of the 8237. This is usually the case. Should an unusual
decoding scheme be in place, the addresses will have to be
recalculated.
Another Example
A 1K block of data starting at location D4200 must
be transferred to an I//O using channel 2. Write the
program to initialize (set-up) the address and count
registers
Another Solution!
There are essentially two steps in a DMA transfer. In the first
step one sets up the 8237. This step usually consists of
setting up many registers. In the second step one requests
DMA action ..... preferably by pulling the hardware line
(DREQ) or by software (Request register). We will simply
show the set-up part for the address and count registers.
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mov ax, 4200h
out 354h , al
mov al, ah
out 354h , al
mov ax, 3ff
out 355h, al
mov al, ah
out 355h, al
; 16-bit offset. D must go in the page register
; send LSB i.e. 00. Assumes byte FF is clear!
; out works with al only
; send MSB i.e. 42
; 1023 in hex.
; send LSB of count
; you know what's up!
; done....for now!
Examples Galore!
What is the command word byte if an area of memory must
be filled with a byte of data stored at another memory
location?
Look at the command word format as you follow the solution
given below:
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D7 = 0 assuming DACK LOW considered active
D6 = 0 assuming DREQ HIGH considered active
D5 = 0 assuming no slow devices
D4 = 0 assuming channel priorities are fixed
D3 = 0 assuming normal timing (only option in memory to
memory!)
• D2 = 0 you don't want to disable the 8237, do you!
• D1 = 1 because we want the pointer to our byte to stay put
• D0 = 1 After all this is a memory -to- memory transfer.
So the answer is 03
The Page Register
Remember the page register? This is not one
of the registers in the 8237. The page register
is an address outside of the 8237 and it holds
the part of the physical address beyond A15
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DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
Channel 0
Channel 1
Channel 2
Channel 3
Channel 5
Channel 6
Channel 7
REFRESH
87H
83H
81H
82H
8BH
89H
8AH
8FH