CMOS Analog Design Using
All-Region MOSFET Modeling
Chapter 11
MOSFET parameter extraction for
design
CMOS Analog Design Using All-Region MOSFET
Modeling
1
Specific current and threshold voltage
gm

ID
2
n t

1 if 
1  ir

VDS
t

1  i f  1  ir  ln
1 if 1
1  ir  1
For VDS/t<<1 we have ifir
gm

ID
1
n t 1  i f
VDS
t

1
i f  ir
2
1 if 1
t
ID

1
ID / IS
2
1 if 1
or
gm
ID

gm
ID
1
m ax
1 if
IS 
2V D S
1 if 1

if 3
t
2V D S
ID
For VDS/t=1/2 and if=3, we have ISID. For VDS/t=1/2 and if=3, more accurate
values for gm/ID and IS are 0.53 times the peak value of gm/ID and 1.13 times the
measured current, respectively .
CMOS Analog Design Using All-Region MOSFET
Modeling
2
Transconductance-to-current ratio of a MOSFET
vs. gate voltage for VDS  Φt/2 and VS=0.
gm
ID

dI D
I D dV G

d ln I D
dV G
CMOS Analog Design Using All-Region MOSFET
Modeling
3
Pinch-off voltage vs. gate voltage
V P
 V S  / t 
1  i f  2  ln

1 if 1

For if=3, the pinch-off voltage is equal to the source voltage.
CMOS Analog Design Using All-Region MOSFET
Modeling
4
Slope factor n=1/(dVP/dVG) vs. gate voltage
CMOS Analog Design Using All-Region MOSFET
Modeling
5
Plot of 1/(n-1)2 vs. pinch-off voltage
n  1   /(2 2 F  V P )
1
( n  1)
2

4V P

2

8 F

2
The slope and the y-intercept of the interpolation line give =0.60 V1/2
and 2F=0.89 V
CMOS Analog Design Using All-Region MOSFET
Modeling
6
Mobility - 1
The dependence of the mobility on the transverse electric field is written
as
0
 
 Q B   Q I 
1   



s

Problem: Determine the mobility variation for cases in which the depletion
charge is much higher than the inversion charge density
Q B  Q B a  Q I ( n  1) / n  Q B a    C o x
 
0
1   V P  2 F
with
2 F  V P
  /s
    C ox
CMOS Analog Design Using All-Region MOSFET
Modeling
7
Mobility-2
n
IS

1
  t2  W / 2 L 
 C ox

VG
+
VS
1   V P  2 F
VS+t/2
 t W / 2 L 
 0 C ox
2
Parameter
VT0
2F

Value
0.552 V
0.89 V
0.60 V1/2

8.8 A
CMOS Analog Design Using All-Region MOSFET
Modeling
0.75 V-1/2
8
Comparison between experiment and the
ACM model in a 0.35 m technology-1
Experiment and ACM model for a long-channel (L=3.2 m) NMOS
transistor in a 0.35 m CMOS technology, with VS=0 and VDS= 13 mV. The
maximum error for currents is around 30% for VG = 3.3 V
CMOS Analog Design Using All-Region MOSFET
Modeling
9
Comparison between experiment and the
ACM model in a 0.35 m technology-2
Plots of experimental and modeled transconductance-to-current
ratio vs. drain current
CMOS Analog Design Using All-Region MOSFET
Modeling
10
Comparison between experiment and the
ACM model in a 0.35 m technology-3
Plot of the experimental and modeled current vs. gate voltage for
a minimum-length NMOS transistor in a 0.35 m technology.
CMOS Analog Design Using All-Region MOSFET
Modeling
11
The Early voltage -1
1
VA

1 dI D
I D dVD

1  I D  VT
I D  VT  V D
V T  V T 0    V SB  V D B 

1 I D L
I D L VD
1
V AC LM
V AD IBL

n t 
ID

 1
 1 

2 
IS



1

V A D IB L
1 I D L
I D L VD
1
V ACLM
1   I D   Y D


I D  L  VD

2
  V D B   SL
F 
V A C LM  2 aL (  L   bi
)
a
 2a 
CMOS Analog Design Using All-Region MOSFET
Modeling
12
The Early voltage -2
Experimental drain and source currents versus drain-to-source voltage
for a minimum channel length NMOS transistor (L=0.4 m) in a 0.35 m
CMOS technology.
CMOS Analog Design Using All-Region MOSFET
Modeling
13
The Early voltage -3
Derivatives of the experimental drain and source currents with respect to
the drain voltage versus drain-to-source voltage for a minimum channel
length NMOS transistor (L=0.4 m) in a 0.35 m CMOS technology.
CMOS Analog Design Using All-Region MOSFET
Modeling
14
The Early voltage -4
Experimental and modeled Early voltages vs. drain-to-source
voltage for a minimum-length NMOS transistor (L=0.4 m) in a 0.35
m CMOS technology
CMOS Analog Design Using All-Region MOSFET
Modeling
15
The Early voltage - 5
Experimental and modeled Early voltages vs. drain-to-source voltage for
transistors M1, M2, M4, and M8, for which the nominal lengths are Lmin,
2·Lmin, 4·Lmin, 8·Lmin, respectively, where Lmin=0.4 m.
CMOS Analog Design Using All-Region MOSFET
Modeling
16
The Early voltage - 6
Fitting parameters extracted for the Early voltage of NMOS transistors
in a 0.35 m CMOS technology.
Transistor  [mV/V]
a [V/m2]
M1
7
2.5 1014
0.1
M2
0.8
2.5 1014
0.1
M4
0.6
2.5 1014
0.1
M8
0.45
2.5 1014
0.1
V AD IBL

n t 
ID

 1
 1 

2 
IS

[V]
 bi  2 F
2
V A C LM
 bi  V D B   SL
 FL 
 2 aL ( 
)
 
a
 2a 
CMOS Analog Design Using All-Region MOSFET
Modeling
17