EZ-COURSEWARE
State-of-the-Art Teaching Tools
From AMS
Teaching Tomorrow’s
Technology Today
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Cache Memory
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Cache
Memory
– Large main memory system: High-capacity, relatively
slow speed dynamic RAMs and EPROMs: 60ns or 70ns
– Processor speed: requires DRAMs with 30 or 40ns,
Latest processors : 10ns 20ns
– Cache memory: small high-speed expensive static RAMs
• Typically from 16KB to 256KB, xMB
• Hit Ratio and Miss Ratio
hit rat e 
number of hit s
100%
number of memoryreferences
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Types of cache organization
– Types of cache organization
• Direct-mapped cache
• N-way set associative cache
• Posted Write
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•
82385DX
Cache
Controller
82385 Cache Controller
– Improves 386 DX performance
• Reduce Average CPU wait states to nearly zero
• Zero wait state posted memory writes
–
–
–
–
–
Hit rates up to 99%
SW transparent
Synchronous Dual Bus Architecture
Maps Full 386 DX address space (4GB)
Flexible Cache Mapping Polices
•
•
•
•
•
Direct Mapped or 2-way Set Associative
Supports Non-cacheable memory space
Unified Cache for Code and Data
132-pin PGA package
Fig 4.44
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82385DX Cache Controller
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Architecture of an 80386DX
microcomputer with an 82385-based
Cache Memory
• Architecture of an 80386DX microcomputer
with an 82385-based Cache Memory
– 386 local bus, 385 local bus, system bus
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Signal Interfaces of the 82385DX
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Signal
Interfaces
of
the
82385DX
• Configuration Input
• M/S (master/slave select):
• 2W/D (two-way set associative or direct-mapped)
• 385/386 Interface signals
• Cache Memory Control Signals
•
•
•
•
CALEN (cache address latch enable)
CT/R (cache transmit/receive)
CS0-CS3(cache chip select) : four 8K bytes SRAMs
COEA, COEB, CWEA, CWEB(cache output enable, cache write
enable)
• 82385 Local bus interface signals
• BBE0-BBE3, BADS, BNA, BLOCK, BREADY
• Bus Arbitration signals
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• 385 bus data transceiver
and address latch control
Connection to the 80386
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Direct-mapped Cache
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Two-way set associative cache
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Direct-Mapped Cache
Organization
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•
Direct-Mapped Cache
386 DX Address
Bus Bit Field
Organization
Cache Address
(1 of 8K Double words)
A31
A15
17-bit Tag
(1 of 217 pages)
A14
Set Address
(1 of 1024 sets)
A5
A4
Line
Select
(1 of 8 lines)
• 4GB:
• 8K double word(32kB) page X 217
• page: 1024 sets of 8 double words (8x32 bits)
• line: 32-bit Double word
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A2
Direct-Mapped Cache
Organization
• Cache Directory Entry
• 17-bit Tag:
• Tag valid bit
• Line valid bits
17-bit tag
Direct-mapped cache directory SET entry format
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Direct-Mapped
Cache
Operation
• Read Hit
• 10-bit set address -- select one of 1024 entries
• 17-bit tag field with the tag
– if Match and Tag and Line Valid bits are set --> hit
• drives the cache
• Read Miss
• Mem -> cache and 386DX
• Line miss - update the line valid bit only
• Tag Miss - the upper address bits overwrite the previously stored
tag
the appropriate line valid bit is set, the other seven line
valid bits are cleared
• Write Hit
• update memory and cache
• directory is unaffected
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Direct-Mapped
Cache
Operation
– Snoop Hit
• cache: unaffected
• the affected line: invalidated
– Cache Flush
• clear all tag valid bits
– Write Miss
• cache: unaffected
• directory: unaffected
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Two-way Set Associative Cache
Organization
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Two-way Set Associative Cache
Organization
• 386 DX Address Bus Bit Field
Cache Address
(1 of 4K Double words)
A31
A14
18-bit Tag
(1 of 218 pages)
A13
A5
Set Address
(1 of 512 sets)
• 4GB:
• Two banks of 4K double word
• 512 sets in each bank
• line: 32-bit Double word
• LRU replacement Algorithm
• LRU bit
• Cache Directory Entry
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A4
A2
Line
Select
(1 of 8 lines)
Two-way Set Associative Cache
• Read Hit
Operation
• The two tags of this set are simultaneously compared with A14A31
Both tag valid bits are checked
Appropriate line valid bits are checked
Update LRU bit
• Read Miss
• Check LRU bit
• Mem-> the bank that the LRU bit points to
• Update Tag, Tag valid bit, line valid bit
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Cache Coherency and Bus
Watching
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