The R3 Model: Device Physics

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TM
NEEDS Workshop
November 18-19, 2014
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•
Original derivation of basic R3 depletion pinching model for
diffused resistors was done at AT&T Bell Labs
− Richard
•
Booth
Original derivation of depletion pinching model for MOS
system (for flapped resistors)
− Jim
Victory
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•
Semiconductor Resistor Basics
− resistor
•
model needs
The R3 Model
− depletion
− velocity
pinching effect (DP)
saturation effect (VS)
− self-heating
− will
effect (SH)
not cover details of pinch-off, CLM, or DIBL models
•
Some details of how the model works
•
Throughout, G=I/V is the large-signal conductance
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•
but don’t think of it
as V=IR
•
in the real world
− SPICE
solves KCL,
not KVL
− biasing
often via
V rather than I
− visualize
in terms
of parallel current
flow paths
•
I=GV often better
− just
not the way we
are taught …
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NOT
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-V
•
-VC
depletion pinching
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-V
-VC
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-V
-VC
•
depletion pinching
•
self-heating
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•
Precision analog circuits need accurate models
•
Resistor ladders
− unequal
resistances from different biases cause systematic errors
in voltage division ratios
− proper
•
connection avoids this, but models should flag problems
Whenever harmonics are important
− resistor
nonlinearity causes signal distortion
− distortion
adds harmonics
− accurate
modeling of deviation from linearity is what is important
− Note:
glitches and wiggles in a model generate harmonics, so
model must be smooth
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•
Depletion pinching (DP)
− affects
both diffused and poly resistors
− accumulation

•
serendipitously depletion pinching model also applies
Velocity saturation (VS)
− only
•
affects diffused resistors
Self-heating effect (SH, i.e. electro-thermal behavior)
− SiO2

thermal conductivity lower than Si
dominant factor for poly resistors
− surprisingly
− unlike
•
can also affect poly resistors
important even for diffused resistors (esp. low rs)
other effects SH is frequency dependent
VS and SH both quadratic in V for low field: I=G(V)V
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VLX
VRX
depletion
regions
L
RC
VL
tb
R/2
R/2
RE
RC
VR
RE
Si substrate
td
junction
VC
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r3: depletion shape
SPICE JFET: linear
data
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tc (V ) = t c0 -
td 0
bi
Wc (V ) = W - 2
 bi  V ( x) -
td 0
bi
 bi  V ( x) -
I ( x) = qN Wc ( x)  tc ( x)
TM
bi

bi

dV
dx
14
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VLX
VRX
depletion
regions
L
RC
VL
tb
R/2
R/2
RE
RC
VR
RE
td
Si substrate
junction
VC

td 0
G = g f 1 bi

TM

 1
2


 t - t  W  bi  Vm - bi
 b d0

15

VLC  VRC
, Vm =
2


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All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
VLX
VRX
L
RC
RC
RE
tb
VL R/2
R/2
VR
RE
td
tox
Si substrate
VC
TM
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2 s
 s V ( x) 
qN
t d ( x) =
2

Vc - V ( x) - VFB
 
 s (V ) =
1
- 1 ,  =
2

4 

4


2
2q s N

Cox
dV
I ( x) = qN Wc ( x)  tc ( x)
dx
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VLX
VRX
L
RC
RC
RE
tb
VL R/2
R/2
VR
RE
td
tox
Si substrate
VC
qW Ntb
G=
L
TM

2 s  2 4 - VFB  Vm 
s

1 

'
'
 tbCox

 tbCox


18
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G (V ,VC ) =
•
1  r


d p - 2VC  V , g f =
1
r sh Leff 1 - d f d p
models mobility change from VS (and SH) effects
even function of V, r(V=0) =0
Same basic form for diffused and poly resistors
− applies
•
1 - d f
Weff
Zero-bias resistance is 1/G(V=0,VC=0)
− r
•
gf
also for accumulation for poly resistors
dp is very large (100’s to 1000’s of V) for poly resistors
− makes
G essentially linear w.r.t. biases
− cannot separately determine dp and df
•
At V=0 velocity saturation and self-heating effects absent
− determination
of G0(VC)=G(V=0, VC) very important for extraction
of depletion pinching parameters
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•
velocity-field relationship
v
v sat
− E=V/L
•
simplest text-book model (b=1)
− easy
to use analytically
− singular
E
− inaccurate
•
common parabolic form (b=2)
− trickier
− free
− still
to use analytically
v=
of singularity
inaccurate
TM
20
0 E
  E
1  
  Ecr

b

 
 
 
1b
, Ecr =
v sat
0
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•
Best thought of as a mobility reduction factor r
•
Empirical form to fit measured data
− parabolic
=
0
1  r
at low field
− adjustable
parameters

critical field Ecr

corner field Eco

corner “hardness” d
2
 E - Ece 
 
r = 

2
E
Ecr
cr 

d  Ece
2
 E  Ece 
 
 

2
E
Ecr
cr 

d  Ece
2
 Ece  4d  Ece
 
- 

E
Ecr
 cr 
2
2
Ece = Eco
 2d 2 Ecr
- 2d  Ecr
TM
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  E
r = 1  
  Ecr

•
b 1 b

 
 
 
-1
free of singularity
− perfectly
smooth
and symmetric
•
accurate
− should
be, it was
formulated based
on this data set
•
difficult to work
with analytically
− but
asymptote is
simple (linear)
4th order
polynomial for Vsat
− yields
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•
Perimeter component of thermal conductance relatively
greater for narrower resistors
− for
both poly and diffused resistors
W
W
Si substrate
TM
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•
Velocity saturation depends on L only, not W
− decreased
“droop” in G(V) for narrow resistor → less SH
wide resistor
(self-heating is dominant
source of nonlinearity)
TM
narrow resistor
(thermal conductance of edges
significantly reduces self-heating)
24
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R
power
dt
C
RTH
CTH
L
temperature rise
coupled electro-thermal
solution in R3
(diffused resistor model
topology shown)
GTH=1/RTH and CTH have area,
perimeter, and contact components
TM
VC=0, V=6, 9, 12 V (top to bottom)
25
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•
L/W=2.1m/4.2m
•
significantly
affected by all of
DP, VS, and SH
TM
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•
L/W=42m/4.2m
•
significantly
affected by DP
and SH
− TC2
influence is
apparent
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TM
28
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
•
Geometry dependence
•
Temperature dependence
− including
•
for the velocity saturation model parameters
Ability to handle all effects being made arbitrary small
− necessary
− breaks
•
Vsat calculation, have overcome that problem
Addition of DIBL and CLM models
− primarily
•
for depletion pinching effect for poly resistors
for JFETs, not resistors
Noise, operating point quantities, statistical variation (both
global and local)
TM
29
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
•
There is much more to semiconductor resistors than
Ohm’s “law” would have us believe
•
Major physical sources of nonlinearity
− depletion
pinching
− self-heating
− velocity
•
saturation (only for diffused, not poly, resistors)
R3 model includes all these effects
− geometry
•
and temperature dependencies, noise, mismatch
Parameter extraction can be challenging
− algorithms
•
developed over past several years now robust
Accurate modeling necessary for precision analog design
− where
TM
nonlinearities and distortion are important
30
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
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