TO-Leadless in IOL-Test
Ralf Walter
Bologna, September 2014
TO-Leadless vs. D²PAK 7Pin
4.4mm
2.3mm
9.9mm
10.0mm
11.7mm
15mm
Footprint: 115 mm²
Footprint: 150 mm²
25%
~50%
~60%
Footprint
Height
Space
Reduction
Reduction
reduction
More details on parameters of high current
packages
lowest RDS(on)
D²PAK
D²PAK 7pin
TOLL
30V
3.4 mΩ
0.9 mΩ
0.4 mΩ
60V
1.9 mΩ
1.0 mΩ
0.75 mΩ
100V
2.7 mΩ
2.5 mΩ
2.0 mΩ
150V
7.2 mΩ
6.5 mΩ
5.9 mΩ
0.7 mΩ
0.4 mΩ
0.25 mΩ
120A
180 A
300 A
150 mm²
150 mm²
115 mm²
>5 nH
<5 nH
~1 nH
Package Resistance
Current Capability
Footprint
Inductivity
IOL Test
IOL=Intermittent Operating Livetime („Power Cycling“)
Testing conditions acc. AEC Q101
Start temperature
20°C
Temperature rise during cycles
∆T=100K
Current
Applied to the bodydiode for a few seconds to
heat up the chip to the target temperature
Number of tested devices
45
Number of power cycles
15.000 with no failures
Premisses
•
•
cooling down the device needs approximately 3 minutes
a parameter drift of 20% is considered as failure
Measured parameters
All standard parameters according to datasheet:
Leakage currents, VBRDSS, VGSth, RDS(on) etc.
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Chip Temperature acc. AEC Q101
Junction
Temperature
120°C
2
1
15,000
20°C
~3min




1 cycle
15,000 cycles
60,000 cycles
200,000 cycles
~1 month
~3
~1
~4
>1
Time
High Current through
the body diode
heats up the junction
45 samples
minutes
month
months
year
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Page 5
IOL Test acc. AEC Q101
∆T=100K, 15k cycles
Number
of
cycles
The yellow graph is
the
expected/calculated
minimum number of
cycles for other
temperature values
The yellow dot
represents
the IOL Test
acc. AEC Q101
∆T=100K
15,000 cycles
∆T/K
Copyright © Infineon Technologies AG 2013. All rights reserved.
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Use of Graph
Number
of
cycles
Example: A power cycling with a ∆T=50K
(e. g. 20°C70°C)
results in >100,000 cycles
(red circle, calculated)
∆T/K
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Page 7
Applications
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Page 8
Applications
 15 years
 several hours per day
 a few high power pulses per hour
 lot of smaller and medium power pulses per hour
Example high power pulses:
5 high power cycles (∆T=100K) per hour
8h working time per day
250 working days per year
5*8*250…....
10,000 cycles per year
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Page 9
IOL Test Diagram TOLL
(IPT007N06N)
Number
of
cycles
∆T=150K:
60,000 cycles
No failures!
∆T/K
Re-calculated curve shows a significant higher number of expected cycles:
>200,000 vs. 15,000
(for ∆T=100K)
Copyright © Infineon Technologies AG 2013. All rights reserved.
Page 10
TO Leadless vs. D2PAK 7 Pin
The TO Leadless, compared to a D2PAK 7Pin with the same chip
size inside, shows a significantly lower RDS(on) (up to -25% in 60V)
and RthJC, resulting in a much lower chip temperature.
This reduced thermal stress results in a very high reliability of the
TO Leadless
RDS(on),max
[mΩ]
TOLL
D2PAK 7P
0.75
1.0
100V
2.0
2.5
150V
5.9
6.5
60V
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Page 11
Conclusion
 The TOLL is a high reliable package, capable to withstand much
more power cycles than required by AEC Q101, even with a
much higher temperature stress (∆T=150K instead of 100K)
 Test highlighted the weakest point oft this setup: The solder
joint MOSFETPCB
 After 70,000 cycles the test had to be stopped because the
solder joint was damaged
 Under the same load conditions, MOSFETs in TOLL package will
show lower losses resulting in a lower chip temperature, e. g. a
very high reliabilty
 A new test was started in May 2014 with a reduced temperature
stress of ∆T=130K (20°C150°C)
 Test duration is expected to last more than one year (>200,000
cycles)
Copyright © Infineon Technologies AG 2013. All rights reserved.
Page 12