Interrupts, Thermistors,
Opto-isolators and
Phototransistors
Fall 2009
Kipp Schoenwald
Stephen Hunte
Joseph Storey

Interrupts
◦ Vectors and Vector Table
◦ Flow Chart
◦ Applications
 Example 1
 Example 2

Thermistors

Opto-isolators

Phototransistors
◦ Theory
◦ Applications
◦ Theory
◦ Applications
◦ Theory
◦ Applications
Outline
Q: What are interrupts good for?
A: Interrupts provide a means to temporarily suspending current instruction for more
important tasks.
Q: How are interrupts initiated?
A: Interrupts are initiated by one of the following:

Hardware interrupts
◦
◦
◦

Peripherals such as a printer or fax machine
Computer Operator via keyboard, mouse or power on reset button
Another computer
Software interrupts
◦
◦
◦
◦
◦
Timer resets
Timer interrupts
Traps
Request for input or output
Arithmetic overflow error
Q: What is the alternative to interrupt and how does it work?
A: Polling – Polling is an loop that continuously looks at all of the inputs.
Interrupts
Kipp Schoenwald
EXAMPLES:
1. Problem:
Power Fails (someone kicks the power cord out of your
laptop)
Solution:
R/C circuit senses impending power loss and runs an
interrupt routine that can select the battery as the power
supply
2.
Problem:
Car engine overheats
Solution:
Thermal couple senses temperature. Runs a interrupt
routine that turns on warning light
Interrupts
Kipp Schoenwald
Definitions:
1.
Interrupt Service Routine (interrupt
handler): This is a “more important”
instruction code that interrupts your main
program code. The routine is specific to the
type of interrupt called.
2.
Interrupt Vector: This is an address in
memory where the ISR instruction code is
located. It is the starting address of the code.
(Like a pointer)
3.
Interrupt Vector Table: This is a table
indicating the interrupt vector
$FFF6
Interrupts: Vectors
Kipp Schoenwald

The interrupt vector table is located:
◦ Pg 61 of Reference Manual (thick book)
◦ Pg 56 of Device User Guide (medium thick book)
◦ Pg 2 of the Reference Guide (thin book).
Interrupts: Vector Table
Kipp Schoenwald
MON12 interrupt vectors are used. ($0F00-$0FFF )
MON12’s calls ISR’s
specified by the user
in the $0Fxx range
The microcontroller
calls ISR’s specified
in the $FFxx range.
Interrupts: MON12 Vector Table
Kipp Schoenwald
The MON12 Interrupt Table shows both the actual Vector Table addresses, and the Ram
Vector Table addresses
Interrupts: MON12 Vector Table
Kipp Schoenwald
Important
Slide
Hardware Interrupt
Software Interrupt (SWI)
Wait For Interrupt (WAI)
Complete
Current
Instruction
YES
1
Maskable
Mask Set
NO
0
Complete
Current
Instruction
Store MPU Registers to SP
YES
Hardware Interrupt
Wait For Interrupt (WAI)
NO
Maskable
Mask Set
SP -6
Condition Code Register
SP -5
Accumulator B
SP -4
Accumulator A
SP -3
Index Register (MS)
SP -2
Index Register (LS)
SP -1
Program Counter (MS)
SP
Program Counter (LS)
NO
YES
1
Stack Pointer
Set Mask (CCR4) (set to 1)
Condition Code Register
X
0
Load Interrupt Vector into PC
I
Begin Interrupt
Program (ISR)
Clear Mask (CCR4) (set to 0)
Interrupt Vector
Back to
Main Program
Interrupts: Flow
Kipp Schoenwald
Hardware Interrupt
Software Interrupt (SWI)
Wait For Interrupt (WAI)
Complete
Current
Instruction
1.
YES
1
Maskable
Mask Set
NO
0
Complete
Current
Instruction
2.
3.
4.
Store MPU Registers to SP
5.
6.
YES
Hardware Interrupt
Wait For Interrupt (WAI)
7.
NO
Maskable
NO
8.
YES
1
Mask Set
Set Mask (CCR4) (set to 1)
0
Load Interrupt Vector into PC
Begin Interrupt
Program (ISR)
Clear Mask (CCR4) (set to 0)
Back to
Main Program
9.
If I bit in CCR is not set (I=0)
and IRQ goes low for at least
φ2 cycle, the IRQ sequence
is entered.
Internal registers  stored to
RAM (SP).
The IRQ mask bit set (I=1).
Data at FFF2 gets loaded into
PCH
Data at FFF3 gets loaded into
PCL
PC contents go out on
address bus during φ1.
Contents of the location
addressed enter instruction
register and are decoded as
first instruction of interrupt
routine.
If it is a more than 1-byte
instruction, additional bytes
enter MPU for execution. If
not, go to next step
After execution, step 7 is
repeated for subsequent
instructions. This is repeated
until “RTI” is executed.
RTI tells the MPU that service
is complete and that it may
reload the registers and
continue the main program
from where it left off.
Interrupts: Flow: IRQ Example 1
Kipp Schoenwald
Important
Slide
Write a routine to interrupt the MCU after 5ms of elapsed time,
assuming prescaler is 1. Use output compare (OC) five.
TFLG1
TIE EQU
TCTL1
SECONDAD
TCNT
TC5
TIOS
EQU
$004C
EQU
EQU
EQU
EQU
EQU
ORG
SEI
LDAA
STAA
STAA
STAA
LDAB
STAB
compare)*/
LDX
ISR*/
STX
refers to.
 FFE5*/
LDD
ADDD
equals the
STD
CLI
$004E
$0048
$FFE4
$0044
$005A
$0040
$1000
%0010 0000
TIOS
TFLG1
TIE
/*OC5 flag*/
/*OC5 enable*/
/*OC5 condition*/
/*OC reference location*/
/*counter*/
/*OC5*/
/*timer input capture or output compare select*/
/*begin routine at a chosen address*/
/*set the I bit of the condition code register*/
/*configures port 5 as output compare (default is 0)*/
/*clear previously set OC5 flag*/
/*enable OC5 Interrupt*/
configure ports as input or output
%0000 1100
TCTL1
/*OC condition: PA5 = high (for a successful
#$2000
/*$2000 is the address where you chose to put your
SECONDAD
/*stores this address “pointer” to the address that OC
High byte (20)  $FFE4, and Low byte (00)
TCNT
#$9C40
/*Loads current value of counter*/
/*adds 40,000cycles (5ms) to the current time (this
time when the ISR is to be run)*/
/*stores this value to be compared*/
/*clear the I bit of the condition code register*/
TC5
Interrupts: Applications: Example 2
Kipp Schoenwald

Interrupts
◦ Vectors and Vector Table
◦ Flow Chart
◦ Applications
 Example 1
 Example 2
◦ Priorities
◦ Interrupt Stack

Thermistors

Opto-isolators

Phototransistors
◦ Theory
◦ Applications
◦ Theory
◦ Applications
◦ Theory
◦ Applications
Outline
•
The Stack Pointer Register holds the
location of the top of the stack at all
times.
•
When the CPU detects an interrupt the
contents of the register are pushed on
the stack.
•
After completion of the interrupt the
saved registers are retrieved from the
stack. The first register pushed onto the
stack will be the last register pulled from
the stack.
Interrupts: Stack
• RTN – address of next
instruction in Main Program,
upon return from interrupt.
• X LO and Y LO are the low
bytes of X and Y registers.
• X HI and Y HI are the high
bytes of X and Y registers.
• ACC A and ACC B are the
accumulators.
• CCR is the Code Condition
Register
RTN LO
RTN HI
Y LO
Y HI
X LO
X HI
ACC A
ACC B
CCR
Interrupts: Stack
Joseph Storey
RTN LO
First Pushed In
Last Pulled Off
RTN HI
Stack Pointer
before Interrupt
Higher Address
Y LO
Y HI
X LO
X HI
Last Pushed In
First Pulled Off
ACC A
ACC B
CCR
Interrupts: Stack
Lower Address
Stack Pointer
after Interrupt
Joseph Storey
Interrupt
Types
Presents
Interrupts: Priorities
Joseph Storey
Non-Maskable Interrupts
• 6 Non-Maskable Interrupts
• Always interrupts program
execution
• Priority over Maskable Interrupts.
• Not subject to global masking
• Sets the X and I bit of the CCR
when serviced
Interrupts: Priorities
Joseph Storey
Non-Maskable Interrupts
Priority of Non-Maskable Interrupts
1.POR of RESET pin
2.Clock monitor reset
3.COP watchdog reset
4.XIRQ interrupt
5.Unimplemented instruction trap
6.Software interrupt (SWI)
Interrupts: Priorities
Joseph Storey

Forces MCU to:
Reset
◦ Assume set of initial conditions
◦ Begin executing instructions at an assigned starting
address



Like interrupts, resets have a vector to define
the starting address of code to be run
Unlike interrupts, they do not return to
original code location
Resets have different vectors to allow
execution of individualized code
Interrupts: Priorities
Joseph Storey
When a reset is triggered:
 The address from the vector is loaded into
the program counter
 S, X, and I bits are set in the CCR
 MCU hardware is initialized to reset state
 Check for any interrupts that have
occurred
Interrupts: Priorities
Joseph Storey
Clock Monitor Reset
 Protects against clock failure
 Set by CME control bit
 If enabled, system resets if no clock edges are
detected within a set period.
Computer operating Properly (COP) Reset
 Protects against software failures (infinite loops, etc)
 When enabled (NOCOP bit in CONFIG register), resets
if free-running watchdog timer rolls over $FFFF
 Timer rate is set in the OPTION register. System Eclock is divided by 215 and further scaled by 1, 2, or 4
Interrupts: Priorities
Joseph Storey
XIRQ
Externally triggered
 PE0 pin low = XIRQ interrupt
 Sets X and I bits
 RTI returns the X and I bits to original
states prior to execution

Interrupts: Priorities
Joseph Storey
Opcode Trap and SWI
Very low priority
 Any enabled interrupt source pending
prior to the initialization of Trap or SWI
will take precedence.
 Once process has begun neither can be
interrupted.

Interrupts: Priorities
Joseph Storey
Maskable Interrupts
• 27 Maskable Interrupts
• Sets I bit in CCR when serviced
• Automatically cleared by RTI interrupt
• Follows default priority, but any one Maskable Interrupt can
be elevated using HIPRO (Higher Priority)
Interrupts: Priorities
Joseph Storey
Maskable Interrupts
Priority of Maskable Interrupts
Discusse
d in
Timer
Lecture
1. IRQ
2. Real-Time Interrupt
3. Standard Timer Channel 0
4. Standard Timer Channel 1
5. Standard Timer Channel 2
6. Standard Timer Channel 3
7. Standard Timer Channel 4
8. Standard Timer Channel 5
9. Standard Timer Channel 6
10.Standard Timer Channel 7
11.Standard Timer Overflow
12.Pulse Accumulator A
Overflow
13.Pulse Accumulator Input
Edge
14.SPI transfer Complete
15.SCI system
16.ATD
17.Port J
18.CRG PLL Lock
19.CRG Self Clock Mode
20.Flash
21.CAN Wakeup
22.CAN Errors
23.CAN Receive
24.CAN Transmit
25.Port P
26.PWM Emergency
Shutdown
27.VREG LVI
Interrupts: Priorities
Joseph Storey
IRQ


Only external maskable interrupt signal
IRQE bit on IRQCR Register
◦ IRQE=1: Falling Edge Sensitive
◦ IRQE=0: Low Level-Sensitive
Peripheral Subsystems (all other Maskable Interrupts)


Flag bit and interrupt enable bit
ATD, Timers, PWM, serial communications,
etc.
Interrupts: Priorities
Joseph Storey
Highest Priority Interrupt (HPRIO)
 HPRIO register moves one maskable
interrupt to top of priority list
 Cannot change priority of nonmaskable interrupts
 Procedure to increase priority of
maskable interrupt:
◦ Set I bit to disable maskable interrupts
◦ Write low byte of interrupt vector to HPRIO
◦ Clear I bit to re-enable maskable interrupts
Interrupts: Priorities
Joseph Storey
Address: $001F

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
0
1
1
1
1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
Bit 0
-
PSEL[7:1] – Priority Select Bits (HPRIO)
◦ Selects one interrupts source to be elevated
◦ Can only be written while I-bit in the CCR is set and
maskable interrupts turned off
◦ Write the low byte of the maskable interrupt vector to
HPRIO to elevate that maskable interrupt to the highest
priority
◦ Ex: writing $DE to HPRIO elevates the Standard Timer
Overflow to highest priority (Standard Timer Overflow
vector = $FFDE)
Interrupts: Priorities
Joseph Storey

Interrupts
◦ Vectors and Vector Table
◦ Flow Chart
◦ Applications
 Example 1
 Example 2
◦ Priorities
◦ Interrupt Stack

Thermistors

Opto-isolators

Phototransistors
◦ Theory
◦ Applications
◦ Theory
◦ Applications
◦ Theory
◦ Applications
Outline
Thermistor - Temperature sensitive resistor
Their change in electrical resistance is very large
and precise when subjected to a change in
temperature.
Thermistors exhibit larger parameter change with
temperature than thermocouples and RTD’s.
Thermistor - sensitive
Thermocouple - versatile
RTD – stable
Generally composed of semiconductor materials.
Very fragile and are susceptible to permanent
decalibration.
Thermistor
Stephen Hunte

One of many available probe assemblies
.095” DIA.
MAX.
TEFLON INSULATION
#32 TINNED
COPPER WIRE
3” LONG
TEFLON TUBE
.11 DIA.
MAX.
2” MIN.
Thermistor Probe
Stephen Hunte





Most thermistors have a negative temperature
coefficient (NTC); that is, their resistance decreases
with increasing temperature.
Positive temperature coefficient (PTC) thermistors
also exist with directly proportional R vs. T.
Extremely non-linear devices (high sensitivity)
Common temperature ranges are –100 oF (~-75 oC)
to +300 oF (~150 oC)
Some can reach up to 600 oF
Thermistor Characteristics
Stephen Hunte
• An individual thermistor curve can be very
closely approximated by using the SteinhartHart equation:
T = Degrees Kelvin
1
T
= A
B ln( R)
3

C ln( R)
R = Resistance of
the thermistor
A,B,C = Curve-fitting
constants
V or R
• Typical Graph
Thermistor (sensitive)
RTD (stable)
T
Thermocouple
(versatile)
Thermistor R-T Curve
Stephen Hunte
Temperature Measurement
“Wheatstone bridge” with selector switch to measure
temperature at several locations
Thermistor Applications
Stephen Hunte
•Resistor is set to a desired
temperature (bridge
unbalance occurs)
Temperature Control
variable resistor for setting
desired temperature
•Unbalance is fed into an
amplifier, which actuates a
relay to provide a source of
heat or cold.
relay
thermistor
high gain
amplifier
•When the thermistor senses
the desired temperature, the
bridge is balanced, opening
the relay and turning off the
heat or cold.
Thermistor Applications
• Operation similar to traditional transistors
• Have a collector, emitter, and base
• Phototransistor base is a light-sensitive
collector-base junction
• Small collector to emitter leakage current
when transistor is switched off, called collector
dark current
Phototransistor Background
Stephen Hunte
Phototransistor Package Types
Stephen Hunte
Phototransistor Construction
• A light sensitive collector base p-n junction
controls current flow between the emitter and
collector
• As light intensity increases, resistance
decreases, creating more emitter-base current
• The small base current controls the larger
emitter-collector current
• Collector current depends on the light
intensity and the DC current gain of the
phototransistor.
Phototransistor Operation
The phototransistor must be properly biased
Basic Phototranstor Circuit
Obstacle Avoidance Example
• Adjust baffle length to obtain a
specific detection range
• Use infrared components that
won’t be affected by visible light
• Use ~ 220 ohm resistors for LED’s
• Use multiple sensors in a row to
detect narrow obstacles
Phtotransistor Summary
•
•
•
•
They must be properly biased
They are sensitive to temperature changes
They must be protected against moisture
Hermetic packages are more tolerant of severe
environments than plastic ones
• Plastic packages are less expensive than
hermetic packages
Phtotransistor SUmmary
Stephen Hunte
Optoisolator Background
• Operation similar to relays
• Used to control high voltage devices
• Excellent noise isolation because switching
circuits are electrically isolated
• Coupling of two systems with transmission of
photons eliminates the need for a common
ground
Optoisolator Background
Stephen Hunte
Glass dielectric sandwich separates input
from output
Optoisolator Construction
Stephen Hunte
• Input Stage = infrared emitting diode (IRED)
• Output Stage = silicon NPN phototransistor
Optoisolator Schematic
Stephen Hunte
Contact Info
Kipp Schoenwald
 Stephen Hunte
 Joseph Storey

kipp.schoenwald@gatech.edu
huntesteve@yahoo.com
jstorey3@gatech.edu
References
1.
2.
Wikipedia.org
Bishop R., Basic Microprocessors and the 6800