PERIPHERAL INTERFACING
UNIT III
Mr. S. VINOD
LECTURER
EEE DEPARTMENT
• Study of Architecture and programming of ICs:
8255 PPI,
8259 PIC,
8251 USART,
8279 Key board display controller and
8253 Timer/ Counter – Interfacing with
8085 - A/D and D/A converter interfacing.
Block Diagram of 8255
It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
Data bus buffer:
•This is a tri state bidirectional buffer used to interface the 8255 to system
data bus. Data is transmitted or received by the buffer on execution of input
or output instruction by the CPU.
• Control word and status information are also transferred
through this unit.
Read/Write control logic
This unit accepts control signals ( RD, WR ) and also inputs from address bus and
issues commands to individual group of control blocks
( Group A, Group B).It has the following pins.
a) CS – Chipselect : A low on this PIN enables the
communication between CPU and 8255.
b) RD (Read) – A low on this pin enables the CPU to read
the data in the ports or the status word through data bus buffer.
c) WR ( Write ) : A low on this pin, the CPU can write
data on to the ports or on to the control register through
the data bus buffer.
d) RESET: A high on this pin clears the control register
and all ports are set to the input mode
e) A0 and A1 ( Address pins ): These pins in conjunction
with RD and WR pins control the selection of one of the
3 ports.
Group A and Group B controls
These block receive control from the CPU and
issues commands to their respective ports.
• Group A - PA and PCU ( PC7 –PC4)
• Group B - PCL ( PC3 – PC0)
• Control word register can only be written into
no read operation of the CW register is
allowed.
PORTS
a) Port A: This has an 8 bit latched/buffered O/P and 8
bit input latch. It can be programmed in 3 modes – mode 0,
mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8
bit input latch. It can be programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit
out put latched/buffer. This port can be divided into two 4
bit ports and can be used as control signals for port A and
port B. it can be programmed in mode 0.
Modes of Operation of 8255
• These are two basic modes of operation of 8255. I/O
mode and Bit Set-Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable
I/O ports, while in BSR mode only port C (PC0-PC7)
can be used to set or reset its individual port bits.
• Under the I/O mode of operation, further there are
three modes of operation of 8255, so as to support
different types of applications, mode 0, mode 1 and
mode 2.
• BSR Mode: In this mode any of the 8-bits of port C can be set or
reset depending on D0 of the control word. The bit to be set or reset
is selected by bit select flags D3, D2 and D1 of the CWR as given in
table.
Mode 0
• I/O Modes :
a) Mode 0 ( Basic I/O mode ): This mode is also called
as basic input/output mode. This mode provides
simple input and output capabilities using each of
the three ports. Data can be simply read from and
written to the input and output ports respectively,
after appropriate initialization.
Programming 8255
 Mode 1:
— Ports A and B are programmed as input or output ports
— Port C is used for handshaking
PC4
PC5
PC3
8255
PC2
PC1
PC0
PC6, 7
PA[7:0]
STBA
IBFA
INTRA
PB[7:0]
STBB
IBFB
INTRB
PC7
PC6
PC3
8255
PC2
PC1
PC0
PC4, 5
PA[7:0]
OBFA
ACKA
INTRA
PB[7:0]
OBFB
ACKB
INTRB
Programming 8255
 Mode 2:
— Port A is programmed to be bi-directional
— Port C is for handshaking
— Port B can be either input or output in mode 0 or mode 1
PC7
PC6
PC4
8255 PC5
PC3
PC0
PC0
PC0
PA[7:0]
OBFA
ACKA
STBA
IBFA
INTRA
PB[7:0]
11-15
CONROL WORD
example 1 -Keyboard
11-18
Bouncing Problem
11-19
Bouncing
11-20
example 2 –stepper motor
• Unipolar full step Stepper motor:
• INPUT SEQUENCE: X Y X Y
1100
0110
0011
1001
• 8255 CONTROL WORD: 1 0 0 0 0 0 0 0 =80H
• control register – 0F
• PORT ADDRESS
port A - 0C
port B - 0D
port C - 0E
START:
MVI A, 80
DELAY:
OUT 0F
LOOP:
MVI A, 0C
OUT 0C
CALL DELAY
MVI A, 06
OUT 0C
CALL DELAY
MVI A, 03
OUT 0C
CALL DELAY
MVI A, 09
OUT 0C
JMP START
MVI C, FFH
DCR C
JNZ LOOP
RET
TRAFFIC LIGHT CONTROLLER
• Common Cathode:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 – ON
0 – OFF
uses 8255 .
To make all ports as O/P ports:
Control word 80H
8255 port addresses:
If 8255 Chip is loaded in PCB left port:
Port A
0CH
Port B
0DH
Port C
0EH
Control register Address
0FH
If 8255 Chip is loaded in PCB right port:
Port A
14H
Port B
15H
Port C
16H
Control register Address
17H
S:
L:
MVI A, 80
OUT 0F
MVI C, 03
LXI H, 4200
MOV A, M
OUT 0C
INX H
MOV A,M
OUT 0D
INX H
MOV A, M
OUT 0E
INX H
DCR C
JNZ L
JMP S
DELAY:
S1:
S2:
S3:
MVI B, 05
MVI D ,FF
MVI E, FF
DCR E
JNZ S3
DCR D
JNZ S2
DCR B
JNZ S1
RET
TEST PROGRAM
DATA
MVI A, 80
OUT 0F
MVI 01
OUT 0C
01, 02, 04, 08, 10, 20, 40, 80
LOOP UP TABLE:
Address
4200
4201
4202
4203
4204
4205
4206
4207
4208
Data
8279
Programmable Keyboard/Display
Interface
• A programmable keyboard and display interfacing chip.
• Scans and encodes up to a 64-key keyboard. And Controls up
to a 16 digit numerical display.
• Keyboard section has a built-in FIFO 8 character buffer.
• The display is controlled from an internal 16x8 RAM that
stores the coded display information.
• 8279 has 8 control words to be considered before It is
programmed
I/O Interface
Basic Description of the 8279
• A0: Selects data (0) or control/status (1) for
reads and writes between 8085 and 8279.
Output that blanks the displays.
• CLK: Used internally for timing. Max is 3 MHz.
• CN/ST: Control/strobe, connected to the control
key on the keyboard.
•
Chip select that enables programming,
reading the keyboard, etc.
• DB7-DB0: Consists of bi-directional pins that
connect to data bus from 8085.
I/O Interface
• IRQ: Interrupt request, becomes 1 when a key
is pressed, data is available.
• OUT A3-A0/B3-B0: Outputs that sends data to
the most significant/least significant of display.
•
: Connects to 8085 WR or RD signal,
reads data/status registers.
• RESET: Connects to system RESET.
• RL7-RL0: Return lines are inputs used to sense
key depression in the keyboard matrix.
•Shift: Shift connects to Shift key on keyboard.
• SL3-SL0: Scan line outputs scan both the
keyboard and displays.
8279 INTERNAL ARCTHITECTURE
Architecture and Signal Descriptions of
8279
• I/O Control and Data Buffers : The I/O control section
• controls the flow of data to/from the 8279. The data buffers interface the
external bus of the system with internal bus of 8279.
• The I/O section is enabled only if CS is low. The pins A0, RD and WR
select the command, status or data read/write operations carried out by the
CPU with 8279.
• Control and Timing Register and Timing Control :
• These registers store the keyboard and display modes and other operating
conditions programmed by CPU. The registers are written with A0=1 and
WR=0. The Timing and control unit controls the basic timings for the
operation of the circuit. Scan counter divide down the operating frequency
of 8279 to derive scan keyboard and scan display frequencies.
Architecture and Signal Descriptions of
8279
Scan Counter :
• The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to
be externally decoded to provide the scan lines for keyboard and display
(Four externally decoded scan lines may drive upto 16 displays). In the
decode scan mode, the counter internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on SL0-SL3(Four internally
decoded scan lines may drive up to 4 displays). The keyboard and display
both are in the same mode at a time.
Return Buffers and Keyboard Debounce and Control:
• This section for a key closure row wise. If a key closer is detected, the
keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After
the debounce period, if the key continues to be detected. The code of key is
directly transferred to the sensor RAM along with SHIFT and CONTROL
key status.
Architecture and Signal Descriptions of
8279
FIFO/Sensor RAM and Status Logic: In keyboard or
• strobed input mode, this block acts as 8-byte first-in-first out (FIFO) RAM.
Each key code of the pressed key is entered in the order of the entry and in
the mean time read by the CPU, till the RAM become empty.
• The status logic generates an interrupt after each FIFO read operation till
the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor
RAM. Each row of the sensor RAM is loaded with the status of the
corresponding row of sensors in the matrix. If a sensor changes its state, the
IRQ line goes high to interrupt the CPU.
Display Address Registers and Display RAM : The
• display address register holds the address of the word currently being
written or read by the CPU to or from the display RAM. The contents of
the registers are automatically updated by 8279 to accept the next data
entry by CPU.
Modes of Operation of 8279
The modes of operation of 8279 are as follows
• 1. Input (Keyboard) modes.
• 2. Output (Display) modes.
Input ( Keyboard ) Modes :
8279 provides three input modes. These modes are as follows:
1. Scanned Keyboard Mode : This mode allows a key matrix to be
interfaced using either encoded or decoded scans. In encoded scan, an 8*8
keyboard or in decoded scan, a 4*8 keyboard can be interfaced. The code
of key pressed with SHIFT and CONTROL status is stored into the FIFO
RAM.
2. Scanned Sensor Matrix : In this mode, a sensor array can be interfaced
with 8279 using either encoded or decoded scans. With encoded scan
8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be
interfaced. The sensor codes are stored in the CPU addressable sensor
RAM.
3. Strobed input: In this mode, if the control lines goes low, the data on
return lines, is stored in the FIFO byte by byte.
(i)Scanned Keyboard mode with 2 Key Lockout :
• In this mode of operation, when a key is pressed, a debounce logic comes
into operation. During the next two scans, other keys are checked for
closure and if no other key is pressed the first pressed key is identified.
• The key code of the identified key is entered into the FIFO with SHIFT
and CNTL status, provided the FIFO is not full, i.e. it has at least one byte
free. If the FIFO does not have any free byte, naturally the key data will not
be entered and the error flag is set.
• If FIFO has at least one byte free, the above code is entered into it and the
8279 generates an interrupt on IRQ line to the CPU to inform about the
previous key closures. If another key is found closed during the first key,
the keycode is entered in FIFO.
• If the first pressed key is released before the others, the first will be
ignored. A key code is entered to FIFO only once for each valid depression,
independent of other keys pressed along with it, or released before it.
• If two keys are pressed within a debounce cycle (simultaneously ), no key
is recognized till one of them remains closed and the other is released. The
last key, that remains depressed is considered as single valid key
depression.
(ii)Scanned Keyboard with N-Key Rollover
• In this mode, each key depression is treated independently.
When a key is pressed, the debounce circuit waits for 2
keyboards scans and then checks whether the key is still
depressed. If it is still depressed, the code is entered in FIFO
RAM.
• Any number of keys can be pressed simultaneously and
recognized in the order, the keyboard scan recorded them. All
the codes of such keys are entered into FIFO.
• In this mode, the first pressed key need not be released before
the second is pressed. All the keys are sensed in the order of
their depression, rather in the order the keyboard scan senses
them, and independent of the order of their release.
(iii). Scanned Keyboard Special Error Mode :
• This mode is valid only under the N-Key rollover mode. This mode is
programmed using end interrupt / error mode set command. If during a
single debounce period ( two keyboard scans ) two keys are found pressed ,
this is considered a simultaneous depression and an error flagis set.
• This flag, if set, prevents further writing in FIFO but allows the generation of
further interrupts to the CPU for FIFO read. The error flag can be read by
reading the FIFO status word. The error Flag is set by sending normal clear
command with CF = 1.
(iv)Sensor Matrix Mode :
• In the sensor matrix mode, the debounce logic is inhibited. The 8-byte
FIFO RAM now acts as 8 * 8 bit memory matrix. The status of the sensor
switch matrix is fed directly to sensor RAM matrix. Thus the sensor RAM
bits contains the row wise and column wise status of the sensors in the
sensor matrix.
• The IRQ line goes high, if any change in sensor value is detected at the end
of a sensor matrix scan or the sensor RAM has a previous entry to be read
by the CPU. The IRQ line is reset by the first data read operation, if AI = 0,
otherwise, by issuing the end interrupt command. AI is a bit in read sensor
RAM word.
Output (Display) Modes : 8279 provides two output modes for selecting the
display options. These are discussed briefly.
1. Display Scan : In this mode 8279 provides 8 or 16character multiplexed
displays those can be organized as dual 4- bit or single 8-bit display units.
2. Display Entry : ( right entry or left entry mode ) 8279 allows options for
data entry on the displays. The display data is entered for display either
from the right side or from the left side.
Command Words of 8279
• All the command words or status words are written or read
with A0 = 1 and CS = 0 to or from 8279. This section
describes the various command available in 8279.
1.Keyboard Display Mode Set
3. Read FIFO / Sensor RAM
5. Write Display RAM
7. Clear Display RAM
2. Programmable clock
4. Read Display RAM
6. Display Write Inhibit/Blanking
8. End Interrupt / Error mode
1.Keyboard Display Mode Set
2. Programmable clock
•
•
The clock for operation of 8279 is obtained by dividing the external clock
input signal by a programmable constant called prescaler.
PPPPP is a 5-bit binary constant. The input frequency isdivided by a decimal
constant ranging from 2 to 31,decided by the bits of an internal prescaler,
PPPPP.
If pin 3 of the 8279 is being clocked by a 2 MHz signal, ppppp should be set to
10100 to divide the clock by 20 to yield the proper 100 KHz operating
frequency.
3.Read FIFO / Sensor RAM
4. Read Display RAM
5.Write Display RAM
6. Display Write Inhibit/Blanking
• The IW ( inhibit write flag ) bits are used to mask the individual set as shown
in the below command word. The output lines are divided into two set (
OUTA0 – OUTA3 ) and ( OUTB0 – OUTB3 ), those can be masked by
setting the corresponding IW bit to 1.
• Once a set is masked by setting the corresponding IW bit to 1, the entry to
display RAM does not affect the set even though it may change the
unmasked set. The blank display bit flags (BL) are used for blanking A and B
nibbles.
• Here D0, D2 corresponds to OUTB0 – OUTB3 while D1 and D3
corresponds to OUTA0-OUTA3 for blanking and masking.
• If the user wants to clear the display, blank (BL) bits are available for each
set as shown in format. Both BL bits will have to be cleared for blanking
both the set.
7.Clear Display RAM
8.End Interrupt / Error mode
Rolling Message In Seven Segment
Display
FORMAT FOR SEVEN SEGMENTS:
d
c
B
a
dp
e
g
command word
Common anode:
0 – ON
1 – OFF
1.Keyboard Display Mode Set
2. Write Display RAM
10h
90h
f
START :
LOP1:
DELAY:
LOP3:
LOP2:
LXI H, 412CH
MVI D, 0FH
MVI A, 10H
OUT 01
MVI A, 90H
OUT 01
MOV A, M
OUT 00
CALL DELAY
INX H
DCR D
JNZ LOP 1
JMP START
MVI B, A0
MVI C, FF
DCR C
JNZ LOP2
DCR B
JNZ LOP3
RET
Address
Opcode
Comment
412C
FF
Blank
412D
FF
Blank
412F
FF
Blank
4130
FF
Blank
4131
FF
Blank
4132
FF
Blank
4133
FF
Blank
4134
FF
Blank
4135
98
H
4136
68
E
4137
7A
L
4138
C8
P
4139
FF
Blank
413A
FF
Blank
413B
FF
Blank
413C
FF
Blank
Flashing Message In Seven
Segment Display
START : LXI H, 4200H
MVI D, 06H
MVI A, 10H
OUT 01
MVI A, 90H
OUT 01
LOP:
MOV A, M
OUT 00
INX H
DCR D
JNZ LOP
CALL DELAY
MVI D, 06H
LOOP;
DELAY:
LOP3:
LOP2:
LXI H, 4300H
MOV A, M
OUT 00
INX H
DCR D
JNZ LOOP
CALL DELAY
JMP START
MVI B, FF
MVI C, FF
DCR C
JNZ LOP2
DCR B
JNZ LOP3
RET
Address
Opcode
Comment
4200
98
H
4201
68
E
4202
7A
L
4203
4204
4205
C8
FF
FF
P
Blank
Blank
4300
FF
Blank
4301
FF
Blank
4302
FF
Blank
4303
4304
4305
FF
FF
FF
Blank
Blank
Blank
ACCEPT A KEY AND DISPLAY
MVI B, 08
MVI A, 00
OUT CNT ; set mode and
display
MVI A, 0CC;set clear display
OUT CNT
MVI A, 90 ; write display
OUT CNT
MVI A, 0FF ;clear the display
BACK: OUT DAT
DCR B
JNZ BACK
LOP: IN CNT ; lop for the pressing of key
ANI 07
JZ LOP
MVI A, 40 ; set to read FIFO
OUT CNT
IN DAT
ANI 0F
; get the corresponding
MOV L, A : code from look up table
MVI H, 42
MOV A,M
OUT DAT
JMP LOP
Address
Opcode
4200
OC
9F
4A
0B
4204
99
29
28
8F
4208
08
09
88
38
420C
6C
1A
• CNT C2
• DAT C0
01
00
68
E8
8259
Programmable Interrupt Controller
8259 Programmable Interrupt Controller
• The 8259 programmable interrupt controller
(PIC) adds eight vectored priority encoded
interrupts to the microprocessor.
• It accepts request from the peripheral
equipment, determine which of the incoming
requests is of the highest importance
• Special features of 8259:
•
•
•
•
Eight level priority controller
Expandable to 64 levels
Programmable interrupt modes
Individual request mash capability
It is packaged in a 28-pin DIP, uses NMOS technology and requires a single
a5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead
in handling multi-level priority interrupts.
It has several modes, permitting optimization for a variety of system
requirements
INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt
Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels
which are requesting service; and the ISR is used to store all the interrupt levels which are being
serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set in the IRR. The highest priority
is selected and stroed into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR
The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates
on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
quality.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The V level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input
levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format of
this data depends on the system mode (mPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control
words and status information are transferred through the Data Bus Buffer.
READ/WRITE CONTROL LOGIC
The function of this block is to accept Output commands from the CPU. It contains the Initialization
Command Word (ICW) registers and Operation Command Word (OCW) registers which store the
various control formats for device operation. This function block also allows the status of the 8259A to
be transferred onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device
is selected.
WR (WRITE)
A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In
Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD signals to write commands into the various
command registers, as well as reading the various status registers of the chip. This line can be tied
directly to one of the address lines
.
INTERRUPT SEQUENCE
The events occur as follows in an MCS-80/85 system:
1. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting the
corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259A will also release a CALL instruction code
(11001101) onto the 8-bitData Bus through its D7±0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the
CPU group.
6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address
onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher
8-bitaddress is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the
ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the interrupt sequence.
PROGRAMMING THE 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 8259A in the system must be brought to a
starting point -by WR pulses.
2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes.
These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.
Initialization Sequence
INITIALISATION COMMAND WORDS
ICW1
• A5±A15: Page starting address of service routines .In an MCS 80/85
system, the 8 request levels will generate CALLs to 8 locations equally
spaced in memory. These can be programmed to be spaced at intervals of
4 or 8 memory locations, thus the 8 routines will occupy a page of 32 or 64
bytes, respectively. The address format is 2 bytes long (A0±A15). When
the routine interval is 4, A0±A4 are automatically inserted by the 8259A,
while A5±A15 are programmed externally. When the routine interval is 8,
A0±A5 are automatically inserted by the 8259A, while A6±A15 are
programmed externally.
• T: If LTIM e 1, then the 8259A will operate in the level interrupt mode.
Edge detect logic on the interrupt inputs will be disabled.
• ADI: CALL address interval. ADI = 1 then interval = 4; ADI e 0 then interval
e 8.
• SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1
no ICW3 will be issued.
• IC4: If this bit is setÐICW4 has to be read. IfICW4 is not needed, set IC4 = 0.
ICW 2
ICW 3
This word is read only when there is more than one 8259A in the system and cascading is used, in
which case SNGL e 0. It will load the 8-bit slave register.
The functions of this register are:
• a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in ICW4) a ``1''
is set for each slave in the system. The master then will release byte 1 of the call sequence
(for MCS- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for
8086 only byte 2) through the cascade lines.
• b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits 2±0 identify
the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2
and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus. d only
when there is more than one 8259A in the system and cascading is used, in which
If BUF=0,M/S is to be neglected.
Programmable Interval
Timer 8253
•
•
•
•
•
The Intel 8253 is a programmable counter /
timer chip designed for use as an Intel
microcomputer peripheral. It uses N-MOS
technology with a single +5V supply and is
packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit
counters, each with a counter rate up to 2
MHz . All modes of operation are software
programmable.
Clock This is the clock input for the counter.
The counter is 16 bits. The maximum clock
frequency is 1 / 380 nanoseconds or 2.6
megahertz. The minimum clock frequency is
DC or static operation.
Out This single output line is the signal that
is the final programmed output of the
device. Actual operation of the out line
depends on how the device has been
programmed.
Gate This input can act as a gate for the clock
input line, or it can act as a start pulse,
depending on the programmed mode of the
counter.
Block diagram of 8253
Data Bus Buffer :
• This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the
• address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are
connected to IOR and IOW, respectively. In memory-mapped I/O, these are
connected to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually
connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address.
The control word register and counters are selected according to the signals on
lines A0 and A1.
Control Word Register :
This register is accessed when lines A0 and A1 are at logic 1. It is used to
write a command word which specifies the counter to be used (binary or
BCD), its mode, and either a read or write operation.
Counters :
These three functional blocks are identical in operation. Each counter
• consists of a single, 16 bit, pre-settable, down counter. The counter can
operate in either binary or BCD and its input, gate and output are
configured by the selection of modes stored in the control word register.
The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the actual count
in process.
Programming the 8253/54 :
• Each counter of the 8253/54 is individually programmed by writing a control word
into the control word register (A0 - A1 = 11).
WRITE Operation :
1. Write a control word into control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register.
READ Operation :
In some applications, especially in event counters, it is necessary to read the value
of the count in process. This can be done by two possible methods:
1. Simple Read :
It involves reading a count after inhibiting the counter by controlling the gate
input or the clock input of the selected counter, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
2. Counter Latch Command :
In the second method, an appropriate control word is written into the control
register to latch a count in the output latch, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
MODES OF 8253
•
•
•
•
•
•
Mode 0 : Interrupt on terminal count
MODE 1 : Hardware Retrigger able One-shot
MODE 2 : Rate generator
MODE 3 : Square Wave Rate Generator
MODE 4 : Software Triggered Strobe.
MODE 5 : Hardware triggered strobe (Retrigger able).
Mode 0 : Interrupt on terminal count
• 1) The output will be initially low after the mode set operation.
• 2) After the count is loaded into the selected count Register the output
will remain low and the counter will count.
• 3) When the terminal count is reached the output will go high and
remain high until the selected count is reloaded.
• 1)Gate = 1 enables counting.
• 2) Gate = 0 disables counting.
Let us set channel 0 in mode 0
START:
MVI A, 30
OUT 0CEH
MVI A, 05
OUT 0C8H
MVI A, 00
OUT 0C8H
HLT
Observe, using an CRO that the output of channel 0 is initially low. After giving six
clock pulse the output goes high
MODE 1 : Hardware Retrigger able One-shot
a) Normal operation
1) The output will be initially high
2) The output will go low on the CLK pulse following the rising edge at the
gate input.
3) The output will go high on the terminal count and remain high until the
next rising edge at the gate input.
b) Retriggering
The one shot is retrigger able, hence the output will remain low for the full
count after any rising edge of the gate input.
c) New count
If the counter is loaded during one shot pulse, the current one shot is not
affected unless the counter is retriggered. If retriggered, the counter is
loaded with the new count and the one-shot pulse continues until the new
count expires.
START:
MVI A, 32
OUT 0CEH
MVI A, 05
OUT 0C8H
MVI A, 00
OUT 0C8H
OUT 0D0H
HLT
;triggers gate 0
MODE 2 : Rate generator
This mode functions like a divide by-N counter.
a) Normal Operation
1) The output will be initially high.
2) The output will go low for one clock pulse before the terminal count.
3) The output then goes high, the counter reloads the initial count and the
process is repeated.
4) The period from one output pulse to the next equals the number of input
counts in the count register.
b) Gate Disable
1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).
2) If Gate goes low during an low output pulse, output is set immediately
high. A trigger reloads the count and the normal sequence is repeated.
c) New count The current counting sequence does not affect when the new
count is written. If a trigger is received after writing a new count but
before the end of the current period, the new count will be loaded with
the new count on the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at the end of the
current counting cycle.
Using mode 2, divide the clock preset
at channel 1 by 10
START:
MVI A, 74
OUT 0CEH
MVI A, 0AH
OUT 0CAH
MVI A, 00H
OUT 0CAH
HLT
;channel 1 in mode 2
;LSB of count
;MSB of count
Mode 3 Square Wave Rate Generator
a)Normal operation
1) Initially output is high.
2) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the
counter reaches terminal count, the state of the output is changed and the counter is
reloaded with the full count and the whole process is repeated.
3) If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After
timeout, the output goes low and the full count is reloaded. The first clock pulse (following
the reload) decrements the count by 3 and subsequent clock pulse decrement the count by
two. Then the whole process is repeated. In this way, if the count is odd, the output will be
high for (n+1)/2 counts and low for (n-1)/2 counts.
b) Gate Disable
If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output is low,
output is set high immediately. After this, When Gate goes high, the counter is loaded with
the initial count on the next clock pulse and the sequence is repeated.
c) New Count
The current counting sequence does not affect when the new count is written. If a trigger is
received after writing a new count but before the end of the current half-cycle of the square
wave, the counter will be loaded with the new count on the next CLK pulse and counting will
continue from the new count. otherwise, the new count will be loaded at end of the current
half-cycle.
To generate a square wave of
frequency 150 KHz at channel
START:
MVI A, 36
OUT 0CEH
MVI A, 0A
OUT 0C8H
MVI A, 00
OUT 0C8H
HLT
Vary the frequency by varying the count . Here the maximum count is FFFF. Thus with
the clock frequency of 1.5 MHZ, which corresponds to 0.6 micro sec
MODE 4 : Software Triggered Strobe
a) Normal operation
1) The output will be initially high
2) The output will go low for one CLK pulse after the terminal count (TC).
3) And become high again
b) Gate Disable
• If Gate is one the counting is enabled otherwise it is disabled. The Gate
has no effect on the output.
c) New count
• If a new count is written during counting, it will be loaded on the next CLK
pulse and counting will continue from the new count. If the count is two
byte then
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be loaded on the next CLK
pulse.
MODE 5 : Hardware triggered strobe
Retriggerable
a) Normal operation
• 1) The output will be initially high.
• 2) The counting is triggered by the rising edge of the Gate.
• 3) The output will go low for one CLK pulse after the terminal count (TC).
b) Retriggering
If the triggering occurs on the Gate input during the counting, the initial count is
loaded on the next CLK pulse and the counting will be continued until the terminal
count is reached.
• c) New count
•
If a new count is written during counting, the current counting sequence will
not be affected. If the trigger occurs after the new count is written but before the
terminal count, the counter will be loaded with the new count on the next CLK
pulse and counting will continue from there.
ADC
• ADC0808/ADC0809 8-Bit μP Compatible A/D Converters with
8-Channel Multiplexer
• The 8-bit A/D converter uses successive approximation as the
conversion technique.
• The 8-channel multiplexer can directly access any of 8-singleended analog signals.
• Key Specifications:
Resolution 8 Bits
Single Supply 5 VDC
Low Power 15 mW
Conversion Time 100 μs
successive approximation
The successive approximation circuit typically consists of four block:
– A sample and hold circuit to acquire the input voltage (Vin).
– An analog voltage comparator that compares Vin to the
output of the internal DAC and outputs the result of the
comparison to the successive approximation register (SAR).
– A successive approximation register block designed to supply
an approximate digital code of Vin to the internal DAC.
– An internal reference DAC that supplies the comparator with
an analog voltage equivalent of the digital code output of
the SAR for comparison with Vin.
The successive approximation register is initialized so that the (MSB) is equal
to a digital 1. This code is fed into the DAC which then supplies the
analog equivalent of this digital code (Vref/2) into the comparator
circuit for comparison with the sampled input voltage. If this analog
voltage exceeds Vin the comparator causes the SAR to reset this bit;
otherwise, the bit is left a 1. Then the next bit is set to 1 and do the
same test, continuing this binary search until every bit in the SAR has
been tested. The resulting code is the digital approximation of the
sampled input voltage and is finally output by the DAC at the end of the
conversion (EOC).
Program for analog to digital conversion
LOOP:
MVI A, 10H
OUT CE
MVI A, 18H
OUT CE
MVI A, 01
XRA A
XRA A
XRA A
XRA A
MVI A, 00
IN D8
ANI 01
CPI 01
JNZ LOOP
INC0
STA 4200
HLT
; CHANNEL 0
; CONTROL WORD
;START PULSE
;STOP PULSE
;END OF CONVERSION
Program for digital to analog conversion
square wave
START:
MVI A, 00
OUT C0H
CALL DELAY
MVI A, FF
OUT COH ; port address DAC
CALL DELAY
JMP START
DELAY:
L1:
L2:
MVI B, 05
MVI C, 0FFH
DCR C
JNZ L2
DCR B
JNZ L1
RET
Program for digital to analog conversion
Saw tooth wave form
START:
L1:
MVI A, 00
OUT 0C0H ; port address of DAC
INR A
JNZ L1
Program for digital to analog conversion
Triangular waveform
START:
L1:
L2:
MVI L, 00H
MOV A, L
OUT C0H
INR L
JNZ L1
MVI L, 0FFH
MOV A, L
OUT C0
DCR L
JNZ L2
JMP START
Universal Asynchronous Receiver
Transmitter
(UART - 8251)
Synchronous vs. Asynchronous
A communication protocol is a convention for data transmission that include
such functions as timing, control, formatting, and data presentation. There
are two categories depending on the clocking of the data on the serial link:
•
Synchronous protocols--each successive datum in a stream of data is
governed by a master clock and appears at a specific interval in time.
• Asynchronous protocols--successive data appear in the data stream at
arbitrary times, with no specific clock control governing the relative delays
between data.
There are special IC chips made for serial data communications. These chip is
called UART (universal asynchronous receiver transmitter) and USART
(universal synchronous-asynchronous receiver-transmitter) 8251.
Transfer Types
•
•
DTE
–
–
DCE
–
–
–
data terminal equipment
e.g. computer, terminal
data communication equipment
connects DTE to communication lines
e.g. modem
• RS-232C
A widely accepted interface standard originally developed to foster data communication on
public telephone network through a modem
This has been adapted to the communication of terminals (PCs) directly to computers.
DTE Connections
25-Pin RS232 Connector
9-Pin RS232 Connector
TTL to RS-232
RS-232 Frame Format
Example
0 b0 b1
Start bit
…
ASCII
bn p s1 s 2
Parity
111101000001111
Idle
A
Stop bit
8251 Block Diagram
• The UART is a universal asynchronous receiver/transmitter, which is
modeled on the real-world Intel® 8251 peripheral interface adapter
component. In the model we are considering, the UART consists of three
main blocks.
• a serial transmit block
• a serial receive block and
• a CPU Interface (I/F) block.
Mode Instruction (Asynchronous)
Mode Instruction (Synchronous)
Command Register
Status Register