Micro transductors ’08
Low Power VLSI Design 1
Dr.-Ing. Frank Sill
Department of Electrical Engineering, Federal University of Minas Gerais,
Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
franksill@ufmg.br
http://www.cpdee.ufmg.br/~frank/
Agenda

Recap

Why do we worry about power?

Metrics

Where does power go in CMOS?

How can we reduce the power dissipation? (1st
part)
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Recap: Transistor Geometrics
Gate
Drain
Source
polysilicon
gate
W
Gate-width
tox
L
Bulk
tox – thickness of oxide layer
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Gate length
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Recap: Logic Gates

Task (e.g. calculation)

Transfer into Logic Gates
(Synthesis)

Gate characteristics:


Delay

Power dissipation

more ...
Y = A+B
Gates realized by transistors
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Recap: CMOS Scheme
VDD
PUN
IN1
…
INx
(supply voltage)
PUN – Pull-up Network
PDN – Pull-down Network
OUT
PDN
GND
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(ground)
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Transistor as Water-tap cont’d
Voltage (Volt, V)
Water pressure (bar)
Current (Ampere, A)
Water quantity per second (liter/s)
0 Volt
1 Volt
1 Volt
1 Volt
1 Volt
1 Volt
0 Volt
1 Volt
1 Volt
1 Volt
0 Volt
0 Volt
0 Volt
1 Volt
-
-
-
-
Source: Timmernann, 2007
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Recap: RC-Delay Model

Simple but effective delay model

Use equivalent circuits for MOS transistors

Ideal switch

Transistor capacitances

ON resistance ( = when transistor is conducting (=ON)
 channel between Drain to Source acts as resistor)

Delay t ~ R*C
CP,gate
CP,gate
Cout
CN,gate
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CN,gate
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X
RN,DS
Cout
7
Sizing

Increasing Width
 Resistance get down
 Increasing current
 Decreasing delay 

BUT
 Capacitance increase too
 Internal capacitances increase 
+ Output load of previous gates increases 

Chain of Inverters: Optimum result (for speed) at equal
fanout!
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Trend: Performance
1000000
100000
Pentium® 4 proc
10000
1 TIPS
1000
MIPS
100
10
1
386
Pentium® proc
8086
0,1
0,01
1970
8080
1980
1990
2000
2010
2020
Source: Moore, ISSCC 2003
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Trend: Power
Source: Moore, ISSCC 2003
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Trend: Power Density
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
100
Nuclear
Reactor
Prescott
Pentium®
8086 Hot Plate
10 4004
P4
8008 8085
Pentium®
386
286
486
8080
1
1970
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1980
1990
Year
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2000
2010
Source: Moore, ISSCC 2003
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Problems of High Power Dissipation

Continuously increasing
performance demands

Increasing power dissipation of
technical devices

Today: power dissipation is a main
problem
 High Power dissipation leads to:
 Reduced time
of operation
 High efforts for cooling
 Higher weight (batteries)
 Increasing operational costs
 Reduced mobility
 Reduced reliability
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Problems: Cooling
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Problems: Cooling cont’d
Solution?
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Chip Power Density Distribution
Power Map
On-Die Temperature

Power density is not uniformly distributed across the chip

Silicon is not a good heat conductor

Max junction temperature is determined by hot-spots

Impact on packaging, cooling
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„The Internet is an Electricity Hog“
Badische Zeitung, 2003

Energy for the internet in 2001 in Germany:
6.8 Bill. kWh = 1.4 % of total energy consumption
 2.35 Bn. kWh for 17.3 Mill. Internet-PCs
 1.91 Bn. for servers
 1.67 Bn. for the network
 0.87 Bn. for USV


Rate of growth (at the moment): 36 % per year
Prognosis: 2010 33 Bn. kWh



> 6 % total energy consumption
> 3 medium nuclear power plants
World: 400 Mill. PCs  0.16 PW (P = Peta=1015)
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Dissipation in a Notebook
Peripherals
Processing
ASICs
Disk
Display
Power supply
Battery
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programmable µPs
or DSPs
Memory
Communication
DC-DC
converter
WLAN
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Ethernet
17
Examples for Energy Dissipation
Energy dissipation in a notebook
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Energy dissipation a PDA
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Battery Capacity
Generalized Moore‘s Law
Intel beats Varta
Capacity of batteries
2% - 6% Increase per year
(up to year 2000)
Source: Timmernann, 2007
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Current Progresses
Batter.
20 kg

Factor 4 in the last 10 years  still much too less
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Metrics: Energy and Power

Energy




Measured in Joules or kWh
“Measure of the ability of a system to do work or produce a
change”
“No activity is possible without energy.”
Power




Measured in Watts or kW
“Amount of energy required for a given unit of time.”
Average power
 Average amount of energy consumed per unit time
 Simplified to "power" in clear contexts
Instantaneous power
 Energy consumed if time unit goes to zero
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Metrics: Energy and Power cont’d

Instantaneous Electrical Power P(t)
 P(t)
= v(t) * i(t)
 v(t): Potential difference (or voltage drop) across
component
 i(t): Current through component

Electrical Energy
E

= P(t) * t = v(t) * i(t) * t
Electrical Energy in CMOS circuits
 Energy
= Power * Delay
 Why?
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Consumption in CMOS

Voltage (Volt, V)
Water pressure (bar)

Current (Ampere, A)
Water quantity per second (liter/s)

Energy
Amount of Water
1
CL
0
Energy consumption is proportional to capacitive load!
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Consumption in CMOS cont’d

Voltage (Volt, V)
Water pressure (bar)

Current (Ampere, A)
Water quantity per second (liter/s)

Energy
Amount of Water
1
CL
0
Energy for calculation only consumed at 0→1 at output
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Energy and Instantaneous Power
INV1:
High instantaneous
Power (bigger width)
CL
 Same Energy (Cin ingnored)
 INV1 is faster
INV2:
Low instantaneous
power
CL
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td1 td2
25
Metrics: Energy and Power cont’d
Power is height of curve
Watts
Approach 1
Approach 2
time
Energy is area under curve
Watts
Approach 1
Approach 2
time
Energy = Power * time for calculation = Power * Delay
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Metrics: Energy and Power cont’d

Energy dissipation
 Determines
 Sets

battery life in hours
packaging limits
Peak power
 Determines
 Impacts
power ground wiring designs
signal noise margin and reliability
analysis
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Metrics: PDP and EDP

Power-Delay Product
 Power
 Quality

P, delay tp
criterion PDP = P * tp [J]

P and tp have some weight

Two designs can have same PDP, even if tp = 1 year
Energy-Delay Product
 EDP
= PDP * tp = P * tp2
 Delay tp
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has higher weight
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Energy and Power

Average Power direct proportional to Energy
 In Following: Power means average power
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Where Does Power Go in CMOS?

Dynamic Power Consumption


Short Circuit Currents


Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leakage

Leaking diodes and transistors
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Dynamic Power Consumption
VDD
Vin
Vout
CL
f01= α * f
Pdyn = CL * VDD2 * P01 * f
P01 : probability for 0-to-1 switch of output
f : clock frequency
α : activity
Data dependent - a function of switching activity!
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Short Circuit Power Consumption
VDD
Vin
Isc
Vout
CL
tsc
GND

Finite slope of input signal

During switching: NMOS and PMOS transistors are conducting for
short period of time (tsc)

Direct current path between VDD and GND
Psc = VDD * Isc * (P01 + P10 )
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Leakage Power Consumption
VDD
Gate
Igate
Source
Igate
Isub
Drain
SiO2
Isub
L
CL

GND

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Most important Leakage currents:

Subthreshold Leakage Isub

Gate Oxide Leakage Igate
Pleak = Ileak * VDD ≈ (Isub + Igate)* VDD
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Power Equations in CMOS
P = α f CL VDD2 + VDD Ipeak (P01 + P10 ) + VDD Ileak
Dynamic power
(≈ 40 - 70% today
and decreasing
relatively)
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Short-circuit power
(≈ 10 % today and
decreasing
absolutely)
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Leakage power
(≈ 20 – 50 %
today and
increasing)
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Levels of Optimization
Speed
> 70 %
Seconds
> 50 %
40-70 %
Minute
25-50 %
25-40 %
Minutes
15-30 %
Gate
15-25 %
Hour
10-20 %
Transistor
10-15 %
Hours
5-10 %
MEM
System
ALU
MP3
Algorithm
Architecture
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MEM
Savings
T1
T
T
S
+
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Error
nach Massoud Pedram
35
Lowering Dynamic Power

Reducing VDD has a quadratic effect!
 Has
a negative effect on performance especially as VDD
approaches 2VT

Lowering CL
 Improves
 Keep

performance as well
transistors minimum size
Reducing the switching activity, f01 = P01 * f
 A function
 Impacted
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of signal statistics and clock rate
by logic and architecture design decisions
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Transistor Sizing for Power Minimization
Lower Capacitance
Higher Voltage
Small W’s
To keep
performance
Large W’s
Higher Capacitance
Lower Voltage

Larger sized devices: only useful only when interconnects dominate

Minimum sized devices: usually optimal for low-power
Source: Timmernann, 2007
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Logic Style and Power Consumption

Voltage decreases:
Power-delay product
improves

Best logic style
minimizes power-delay
for a given delay
constraint

New Logic style can
reduced Power
dissipation
(if possible / available !)
Source: Timmernann, 2007
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Transistor Reordering

Logically equivalent CMOS gates may not have
identical energy/delay characteristics
y  (a1  a2)b
a2
a1
b
b
a1
y
b
A
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a2
B
y
y
a1
a2 a1
a1
a2
y
b
a1
b
b
a2
a2
a1
a2
b
a1
a2
b
C
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D
39
Transistor Reordering cont’d
Normalized Pdyn
Activity (transitions / s)
(A)
(B)
(C)
(D)
max. savings
0.81
0.84
0.98
1.0
19%
0.58
0.53
0.53
0.48
10%
Aa1 = 10 K
(1)
Aa2 = 100 K
Ab = 1 M
Aa1 = 1 M
(2)
Aa2 = 100 K
Ab = 10 K
 For given logic function and activity:
Signal with highest activity → closest to output
to reduce charging/discharging internal nodes
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Impact of rise/fall times on short-circuit currents
VDD
VDD
ISC 
Vin
ISC IMAX
Vout
CL
Large capacitive load
Vout
Vin
CL
Small capacitive load
Source: Timmernann, 2007
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Isc as a Function of CL
2,5
x 10-4
 At small load capacitance
CL  large Isc
 But: large CL increases
Pdyn
CL = 20 fF
2
1,5
1
 2nd Possibility:
Minimization of short
circuit dissipation by
matching the rise/fall times
of input and output signals
CL = 100 fF
0,5
CL = 500 fF
0
0
2
4
-0,5
500 ps input slope
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6
x 10-10
 Slope engineering
time (sec)
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Transition Probabilities for CMOS Gates
Example: Static 2 Input NOR Gate
If A and B with same input signal probability:
Truth table of NOR2 gate
A
B
Out
1
1
0
0
1
0
1
0
0
0
0
1
PA=1 = 1/2
PB=1 = 1/2
Then:
POut=0 = 3/4
POut=1 = 1/4
P0→1
= POut=0 * POut=1
= 3/4 * 1/4 = 3/16
Ceff = P0→1 * CL = 3/16 * CL
Source: Timmernann, 2007
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Transition Probabilities cont’d






A and B with different input signal probability:
PA and PB : Probability that input is 1
P1
: Probability that output is 1
Switching activity in CMOS circuits: P01 = P0 * P1
For 2-Input NOR: P1 = (1-PA)(1-PB)
Thus: P01 = (1-P1)*P1 = [1-(1-PA)(1-PB)]*[(1-PA)][1-PB] (see next slide)
P01 = Pout=0 * Pout=1
NOR
(1 - (1 - PA)(1 - PB)) * (1 - PA)(1 - PB)
OR
(1 - PA)(1 - PB) * (1 - (1 - PA)(1 - PB))
NAND
PAPB * (1 - PAPB)
AND
(1 - PAPB) * PAPB
XOR
(1 - (PA + PB- 2PAPB)) * (PA + PB- 2PAPB)
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Transition Probabilities cont’d
Transition Probability of NOR2 Gate as a Function of Input Probabilities
Probability of input signals → high influence on P01
Source: Timmernann, 2007
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Logic Restructuring
 Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P01 = P0 * P1 = (1 - PAPB) * PAPB
0.5
A
B
0.5

(1-0.25)*0.25 = 3/16
W
7/64 = 0.109
X
15/256
C
F
0.5
D
0.5
0.5 A
0.5 B
0.5
C
0.5 D
3/16
Y
15/256
F
Z
3/16 = 0.188
Chain implementation has a lower overall switching activity than
tree implementation for random inputs
 BUT: Ignores glitching effects
Source: Timmernann, 2007
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Input Ordering
(1-0.5x0.2)*(0.5x0.2)=0.09
0.5
A
B
0.2
X
C
0.1
F
(1-0.2x0.1)*(0.2x0.1)=0.0196
0.2
B
X
C
F
0.1
A
0.5
AND: P01 = (1 - PAPB) * PAPB
Beneficial: postponing introduction of signals with
a high transition rate (signals with signal
probability close to 0.5)
Source: Timmernann, 2007
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Glitching
A
B
X
Z
C
ABC
101
000
X
Z
Unit Delay
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Example 1: Chain of NAND Gates
out1
out2
out3
out4
out5
1
...
V (Volt)
6.0
4.0
out2
out4
out6
out8
VDD / 2
2.0
out1
out3
out5
out7
0.0
0
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1
t (nsec)
2
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3
49
Example 2: Adder Circuit
Cin
S14
S15
S0
S1
S2
S Output Voltage (V)
3
S3
2
S4
Cin
S2
S15
VDD / 2
S5
1
S10
S1
S0
0
0
2
4
6
8
10
12
Time (ps)
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How to Cope with Glitching?
0
F1
0
1
F2
0
0
2
F3
0
0
F1
1
F3
0
0
F2
1
Equalize Lengths of Timing Paths Through Design
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