Microprocessor system
architectures – ARMv8
Jakub Yaghob
ARM architecture
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RISC
Large uniform register file
Load/store architecture
Simple addressing modes
Execution states
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AArch64 x AArch32
Architecture profiles
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A – application profile
R – real-time profile
M – microcontroller profile
Execution states – AArch64
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AArch64
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31 64-bit general-purpose registers
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X30 – procedure link
64-bit PC, SPs, ELRs (exception link registers)
32 128-bit SIMD registers
Single instruction set A64
Exception levels EL0-EL3
64-bit virtual addressing
Names each system register with suffix that indicates
the lowest EL with access
PSTATE (Process state)
Execution states – AArch32
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AArch32
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13 32-bit general purpose registers
32-bit PC, SP, LR (link register)
Some registers banked for each execution mode
Single ELR (return from Hyp)
32 64-bit SIMD registers
A32 instruction set – fixed length encoding,
compatible with ARMv7
T32 instruction set – variable-length, compatible with
ARMv7 Thumb
32-bit virtual address
CPSR (current program state register)
Supported data types,
cryptographic extension
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Integer
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Floating point
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B, H, W, D, Q
HP, SP, DP
IEEE 754
Cryptographic extension
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Operates on the vector register file
AES, SHA1, SHA2-256
Memory model
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The ARM memory model supports
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Generating an exception on an unaligned memory access
Restricting access by applications to specified areas of memory
Translating virtual addresses provided by executing instructions
into physical addresses
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AArch64 – 64-bit addressing, TCR (Translation Control Register)
determines VA range, EL0+EL1 have 2 independent VA ranges each
with its own TCR
AArch32 – 32-bit addressing, TCR determines VA range, OS can split
VA range into 2 subranges for EL0+EL1 with separate TCR
Altering the interpretation of multi-byte data between big-endian
and little-endian
Controlling the order of accesses to memory
Controlling caches and address translation structures
Synchronizing access to shared memory by multiple PEs
Application architecture –
AArch64
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31 general-purpose registers R0-R30
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64-bit GP registers X0-X30
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32-bit GP registers W0-W30
Encoding 1Fh for register used as ZR (zero register)
32 vector registers V0-V31
FPCR, FPSR – floating-point status and control
register
SP 64-bit
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X30 procedure link
WSP 32-bit
Current SP
PC 64-bit
Application architecture –
AArch64 – vector registers
Application architecture –
AArch64 – PSTATE
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Process state for EL0
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Data processing flags
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N – negative
Z – zero
C – carry
V – overflow
Exception masking bits
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D – debug mask
A – system error mask
I – IRQ mask
F – FIQ mask
System registers
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Register naming
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General system control registers
Debug registers
Generic timer registers
Performance monitor registers
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Optional
Trace registers
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<register_name>_Elx, x∈{0,1,2,3}
Optional
Generic Interrupt Controller (GIC) CPU interface registers
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Optional
Software control and EL0
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Exception handling
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System instructions for control flow
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WFI – Wait For Interrupt
WFE – Wait For Event
YIELD – hint
Can enter low-power state
Cache management
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Interrupts
Memory system aborts
Undefined instructions
System calls
Secure monitor or Hypervisor traps
Must be enabled by EL1
Debug events
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BKPT – breakpoint
DBG – hint to the debug system
HLT – entry to Debug state
Caches and memory hierarchy
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Point of Unification
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IC, DC see the same copy of a memory
Point of Coherency
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All agents that can access memory are guaranteed to see the same copy
Memory types
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Normal
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Bulk memory operations, R/W, R/O
Device
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Speculative reads forbidden
Additional attributes
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Gathering
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Reordering
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Write can be acknowledged other than at the end point
Shareability
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Preserves access order and synchronization requirements
Early write acknowledgement
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Prevents aggregation of R/W
Non-shareable, inner shareable, outer shareable
Cacheability
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Non-cacheable, write-through cacheable, write-back cacheable
Alignment
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Instruction alignment
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A64 instructions must be word-aligned
Data alignment
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Unaligned access to any Device memory causes an
Alignment fault
Normal memory
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SCTLR_ELx.A – configure unaligned access behavior
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Generate an Alignment fault
Perform an unaligned access
Unaligned access
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Not guaranteed to be atomic
Takes a number of additional cycles
Can abort more times for memory exceptions
Endian support
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Instruction endianness
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A64 instructions are always little-endian
Data endianness
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SCTLR_EL1.E0E – configures endianness for
EL0 at EL1 or higher
Instructions for reverting data in registers
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REV16, REV32, REV64
Synchronization and
semaphores
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Load-exclusive instructions
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Store-exclusive instructions
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STXP, STXR, STXRH, STXRB
Clear-exclusive
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LDXP, LDXR, LDXRH, LDXRB
CLREX
Should scale on MPS
Exception levels
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Exception levels EL0-EL3
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EL0 – unprivileged execution, applications
EL1 – OS kernel
EL2 – supports virtualization of non-secure operation,
hypervisor
EL3 – supports switching between two security states
(secure state, non-secure state), secure monitor
All implementations must include EL0 and EL1
Stack pointer register selection
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SP_ELx
Exception levels
Exception mechanism
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Saved Program Status Register
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Saves PE state on taking exceptions
SPSR_ELx for exception taken to ELx
When returning from an exception, PE state restored
to the state stored SPSR
Exception link registers
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ELR_ELx holds preferred exception return address
Exception vectors
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Vector Base Address Register (VBAR)
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Each Elx
Defines base address for the table at that ELx
System calls
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SVC
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HVC
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Supervisor call exception
EL0 calls OS at EL1
Hypervisor call exception
For EL1 and higher
SMC
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Secure monitor call exception
For EL1 and higher
Virtual Memory System
Architecture
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VMSA
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Provides MMU
MMU translates VAs to PAs independently for
ELx and security states
A64 has 48-bit VA and PA
Address translation system
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VMSAv8-64
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Translation Table Base Register (TTBR)
Translation Control Register (TCR)
Up to four levels of address lookup
IA of up to 48 bits
OA of up to 48 bits
A translation granule size of 4K, 16K, 64K
4K translation granule
16K translation granule
64K translation granule
Translation table entries –
levels 0-2
Translation table entries –
level 3
Attribute fields
MMU faults
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All types of MMU exceptions
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Alignment fault
Permission fault
Translation fault
Address size fault
Synchronous external abort on a translation table
walk
Access flag fault
TLB conflict abort
Translation Lookaside Buffers
(TLB)
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TLB
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Caches results from translation table walks
Global pages
Process-specific pages
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Address Space Identifier (ASID)
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Virtual Machine Identifier (VMID)
Concept of locked entries
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Implementation defined size 8 or 16 bits
Optional for implementation
Maintenance instructions
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TLBI <operation>{,Xt}