Analogue Input/Output

Many sensors & transducers produce voltages representing
physical data.


Many output devices require variable control, not just two
digital logic levels



To process transducer data in a computer requires conversion to digital
form.
To control these devices from a computer requires conversion from
digital to analogue form (usually an analogue voltage).
The conversion from analogue signals to digital values is
performed by Analogue to Digital Converter (ADC)
The conversion from a digital value to an analogue signal is
performed by a Digital to Analogue Converter (DAC).
5-1
DAC function
Parallel DAC
n bit
value
DA Converter
VAgnd
Analogue
output
Vref
Serial DAC would typically have a single data input line and a clock input signal
which would be used to clock in the serial data stream.
Adv. : - Fewer pins.
Disadv. : Slower data transfer.
5-2
Analogue Output


Digital to Analogue Converter (DAC)
DAC Characteristics
= 1/2n where n is the number of bits
 Max. digital value = 2n – 1
 output voltage range – determined by reference voltage
(Vref and AGND)
 Step size in volts = resolution x voltage range
 Max output voltage = (2n – 1)/ 2n x voltage range
 uni-polar / bipolar types
 slew rate – rate of change of output.
 interface – parallel (fast) or serial (slower but uses fewer
connections)
 resolution
5-3
DAC principles – Example 4-bit DAC

Sum currents with operational amplifier
1
d3
2R
R
Vref/2
Vo = - Vref(Rf/Rinput)
4R
Vref/4
0
d2
8R
Vref/8
+
1
d1
1
Vref
d0
Vo
Vo = -(Vref-AGND)(digital value/2n)
16R
Vo α digval/ 2n
Vref/16
AGND
Example: with 4-bit value = 1011
Vo = -Vref(d3/2 + d2/4 + d1/8 + d0/16)
Vo = -Vref(1/2 + 1/8 + 1/16)
Vo = -Vref(11/16)
5-4
Output from DAC
Output
Voltage
VMAX = Maximum output voltage
2n -1
V max  n *Vref
2
where n is number of bits
MAXVAL = Maximum digital value
VMAX
= 2n -1
where n is number of bits
MAXVAL
Digital
Value
5-5
Example DAC device

M AX5722 dual,12-bit, low-power, buffered voltage output, digital-to-analog
converter (DAC) is packaged in a space-saving 8-pin μMAX package (5mm
✕ 3mm).
Ultra-Low Power Consumption
112μA at VDD = +3.6V
135μA at VDD = +5.5V
Wide +2.7V to +5.5V Single-Supply Range
8-Pin μMAX Package
0.3μA Power-Down Current
Guaranteed 12-Bit Monotonicity (±1LSB DNL)
Safe Power-Up Reset to Zero Volts at DAC Output
Three Software-Selectable Power-Down
Impedances (100kΩ, 1kΩ, Hi-Z)
Fast 20MHz, 3-Wire SPI, QSPI, and MICROWIRECompatible
Serial Interface
Rail-to-Rail Output Buffer Amplifiers
Schmitt-Triggered Logic Inputs for Direct
Interfacing to Optocouplers
Wide -40°C to +125°C Operating Temperature
Range
5-6
Audio & LPC 23xx DAC example

Recreate audio
111
110
101
100
011
010
001
000
1


2
3
4
5
6
7
8
9
10
What resolution?
What sampling rate ?
5-7
Analogue Input


Analogue to Digital Converter (ADC)
ADC Characteristics
= 1/2n where n is the number of bits
 Max. digital value = 2n – 1
 input voltage range – determined by the reference voltages
(Vref and AGND)
 Step size in volts = resolution x voltage range
 uni-polar / bipolar types
 interface – parallel (fast) or serial (slower but uses fewer
connections)
 often integrated into microcontrollers.
 resolution
5-8
General ADC function
Analogue
input
Converter
VAgnd


n bit
result
Vref
The analogue input voltage is converted into a value.
The value is dependent on the reference voltages
and the number of bits n.
5-9
Analogue Input

Main types (i.e.methods) of ADC
approximation – good all-rounder
 Flash – fastest type
 Sigma-delta – good for audio
 Dual slope integrating – slow but high resolution with good
noise immunity
 others – Sampling, ramp, charge balancing
 Successive

Characteristics
 resolution
 conversion
method
 conversion time
 input voltage range
 interface – parallel (fast) or serial(fewer connections)
5-10
MCP3208

Features
12-bit resolution
± 1 LSB max DNL
± 1 LSB max INL (MCP3204/3208-B)
± 2 LSB max INL (MCP3204/3208-C)
4 (MCP3204) or 8 (MCP3208) input channels
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100 ksps max. sampling rate at VDD = 5V
50 ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology:
500 nA typical standby current, 2 μA max.
400 μA max. active current at 5V
Industrial temp range: -40°C to +85°C
Available in PDIP, SOIC and TSSOP packages
5-11
Example:8-bit ADC with Vref +5v and 0v VAgnd






Number of steps (values) = 2n = 28 = 256
steps are numbered 0 to 255
step size = reference voltage range / number of steps
= (5v – 0v) / 256 = 19.53125 x10-3v  20mv
number range 0 to 255 corresponds to voltage range
of 0 to  5v
ADC value = (Vin / (Vref – Agnd)) * 256 : remember
max ADC value is 255 so max input voltage that can
be converted accurately is less than 5 volts.
What is the maximum convertible input voltage?
5-12
8-bit ADC with 5v reference
ADC
value
255
ADC
value
4
3
2
1
V
10mv
30mv 50mv 70mv
20mv
40mv
60mv
Volts
0
4.98
5-13
Cont.
ADC value
4
3
2
1
Volts
0
10mv
30mv
50mv
70mv
20mv
40mv
60mv
80mv
5-14
Quantization Error
101
100
011
010
001
0
1
2
3
4
5
6
Each input sample is assigned a quantization interval that is closest to
its amplitude height. If an input sample is not assigned a quantization
interval that matches its actual height, then an error is introduced into
the conversion process.
This error is called quantization error/noise.
Reducing quantization error



One way to reduce quantization noise is to increase the amount of
quantization intervals.
The difference between the input signal amplitude height and the
quantization interval decreases as the quantization intervals are increased
(increases in the intervals decrease the quantization noise).
Solved by increasing the ADC resolution (number of bit) in proportion to the
increase in quantization intervals.
8 80
80
7 70
70
6 60
60
5 50
50
4 40
40
3 30
30
2 20
20
1 10
10
0
0
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
0
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
Analogue Input Example

Example - The LM35 series are
precision integrated-circuit
temperature sensors, whose
output voltage is linearly
proportional to the Celsius
(Centigrade) temperature.
•
•
Calibrated directly in ° Celsius (Centigrade)
Linear + 10.0 mV/°C scale factor
•
0.5°C accuracy guarantee able (at +25°C)
•
Rated for full -55° to +150°C range
•
Suitable for remote applications
•
Low cost due to wafer-level trimming
•
Operates from 4 to 30 volts
•
Less than 60 µA current drain
•
Low self-heating, 0.08°C in still air
•
Nonlinearity only ±¼°C typical
•
Low impedance output, 0.1 Ohm for 1 mA load
5-17
LM35 & LPC23xx Interface Example


Max voltage from sensor = 10mV×150 = 1.5V
+5V
8

ADC range (LPC23xx) 0V to + 3.3 V
LM35 Linear + 10.0 mV/°C scale factor
Use a basic Centigrade temperature sensor +2°C to +150°C
LM35 Input
0 - 1.5V
3
2
+
0 - 3V
1
4

Scale the input voltage accordingly to
match input the range of the ADC
5-18
LM35 & LPC23xx Interface Example



step size = reference voltage range / number of steps
= (3.3v – 0v) / 1024 = 3.22265625 x10-3v
Every 1°C is now equivalent to 20.0 mV
Temperature resolution > 0.2°C
8
+5V
0 - 1.5V
3
2
+
0 - 3V
AI0
1
4
LM35 Input
LPC23xx
5-19
ADC input

Good practice to
 Limit
the voltage range (input protection)
 Filter the signal
D41
From
sensor EXT_TEMP
C133
1u
+5V
R162
TP37
TP_EXT_TEMP_F
R163
U38C
10
8.87k
BAT54S/SOT
9
15k
C134
0.47u
+
8
-
EXT_TEMP_F
To ADC
input
MCP604
5-20
ADC Block diagram
Interface to uP
Interrupt request
Conversion
Control
AN0
AN1
ANn
M
u
t
i
p
l
e
x
e
r
Busy
Start
conversion
Sample
& Hold
Converter
VAREF
Result
Register
VAGND
Reference voltage
5-21
ADC – principle of operation
1.
2.
3.
4.
5.
The voltage is presented to the ADC input.
The ADC is sent a signal to start conversion
While the conversion takes place the input voltage
should remain stable.
The ADC outputs a signal to indicate that it is busy
doing the conversion and should not be disturbed.
When the conversion is completed the ADC makes
the result available and outputs a signal to indicate
that the conversion has completed (e.g remove the
busy signal)
5-22
Multiplexer and Sample/Hold

To convert several analogue inputs
1. use an ADC for each input or more usually …
2. use one ADC and switch the inputs through a multiplexer


requires selection of input before each conversion is started and a
short delay is required before conversion started to allow
switching to occur and signal to settle.
Sample and Hold (S&H)





while conversion takes place voltage must remain stable
sample voltage – input connected to S&H
voltage held on a capacitor
sample time – charging time of capacitor
input signal disconnected from S&H
5-23
Summary



Analogue inputs are often required in embedded
applications and so ADCs are integrated into most
microcontrollers (DACs less so)
ADCs and DAC also exist as standalone IC devices often specialist devices e.g. High speed or high
resolution ADCs, fast DACs for video output.
Main characteristics of interest is
 resolution
- number of bits
 voltage range
 ADC - conversion time
 DAC - slew rate
5-24
ADC on the LPC23xx

LPC23xx ADC Features








10 bit successive approximation analogue to digital converter.
Input multiplexing among 6 pins or 8 pins.
Power down mode.
Measurement range 0 to 3.3 V.
10 bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
5-25
Using the ADC


The ADC like all other peripherals is accessed through a
group of associated registers. (see pages 575ff of the user
manual for a detailed description)
As an example we will look at the A/D Control Register
(AD0CR)
5-26
AD0CR
This bit is significant only when
the START field contains 010111. In these cases:1- Start
conversion on a falling edge on
the selected CAP/MAT signal. 0
Start conversion on a rising edge
on the selected CAP/MAT signal
1 The A/D
converter is
operational. 0 The A/D converter
is in power-down
mode.
0- Conversions are software controlled and require
11 clocks. 1- The AD converter does repeated
conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by
1s in the SEL field. The first conversion after the
start corresponds to the least-significant 1 in the
SEL field, then higher numbered 1 bits (pins) if
applicable. Repeated conversions can be
terminated by clearing this bit, but the conversion
that’s in progress when this bit is cleared will be
completed.
Selects which of the AD0.7:0 pins is
(are) to be sampled and converted.
For AD0, bit 0 selects Pin AD0.0,
and bit 7 selects pin AD0.7. In
software-controlled mode, only one
of these bits should be 1. In
hardware scan mode, any value
containing 1 to 8 ones. All zeroes is
equivalent to 0x01.
AD0CR Bit number
31 30 29 28
R
R
R
R
27 26 25 24 23 22 21 20 19 18 17
EDGE
START
R
R
PDN R
When the BURST bit is 0, these bits control whether and when an
A/D conversion is started:
000 No start (this value should be used when clearing PDN to 0).
001 Start now.
010 Start when the edge selected by bit 27 occurs on
P2.10/EINT0.
CLKS
16 15 14 13 12 11 10
BURST
CLKDIV
This field selects the number of
clocks used for each conversion in
Burst mode, and the number of
bits of accuracy of the result in the
LS bits of ADDR, between 11
clocks (10 bits) and 4 clocks (3
bits).
000 11 clocks / 10 bits
001 10 clocks / 9 bits
011 Start when the edge selected by bit 27 occurs on
P1.27/CAP0.1.
100 Start when the edge selected by bit 27 occurs on MAT0.1.
101 Start when the edge selected by bit 27 occurs on MAT0.3[1].
110 Start when the edge selected by bit 27 occurs on MAT1.0.
111 Start when the edge selected by bit 27 occurs on MAT1.1.
9
8
7
6
5
4
3
2
1
0
SEL
The APB clock (PCLK) is divided by (this
value plus one) to produce the clock for the
A/D converter, which should be less than or
equal to 4.5 MHz. Typically, software
should program the smallest value in this
field that yields a clock of 4.5 MHz or
slightly less, but in certain cases (such as a
high-impedance analog source) a slower
clock may be desirable.
010 9 clocks / 8 bits
011 8 clocks / 7 bits
100 7 clocks / 6 bits
101 6 clocks / 5 bits
R = Reserved, user software should not
write or read ones to reserved bits.
110 5 clocks / 4 bits
111 4 clocks / 3 bits
5-27
AD0CR
AD0CR Bit number
31 30 29 28
R
R
R
R
R
R
R
R
27
0
EDGE
26 25 24 23 22 21 20 19 18 17
0
0
0
START
AD0CR = ( 0x01 << 0 ) |
R
R
R
R
1
R
PDN R
0
0
CLKS
0
16
0
BURST
15 14 13 12 11 10 9
0
0
0
0
1
0
1
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
1
CLKDIV
SEL
/* SEL=1,select channel 0~7 on ADC0 */
( ( Fpclk / ADC_Clk - 1 ) << 8 ) | /* CLKDIV = Fpclk / 1000000 - 1 */
( 0 << 16 ) |
/* BURST = 0, no BURST, software controlled */
( 0 << 17 ) |
/* CLKS = 0, 11 clocks/10 bits */
( 1 << 21 ) |
/* PDN = 1, normal operation */
( 0 << 24 ) |
/* START = 0 A/D conversion stops */
( 0 << 27 );
/* EDGE = 0 (CAP/MAT singal falling,trigger A/D conv */
5-28
Enable the ADC input pins

Before using the ADC the appropriate pins must be set as ADC inputs. This
is accomplished using the PINSEL register(s)
PINSEL1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
4
PINSEL1 |= 0x00004000; // Select only ADC channel 0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
5-29
Reading the ADC

See example programs!
5-30
Example question

A 5 bit ADC is used to encode an analogue signal in
the range 0V to +5V for linear PCM encoding
determine:
 The
step size
 Calculate the percentage resolution
 Calculate the dynamic range in dB
 Calculate the input voltage level corresponding 10110.
Solution
1.The step size
Number of steps  25  32
step size 
50
 156 .25 10 3V
32
2. Calculate the percentage resolution
1
% Resolution   100  3%
32
Solution
3 Calculate the dynamic range in dB
20 log25  30.1dB
4 Calculate the input voltage level corresponding 10110
10110  22 Dec
22  0.3125  3.4375V
5-33
Voice signal
Signal
Bandpass Filtering
Energy Distribution for
Human Speech
0 Hz
300 Hz
3,400 Hz
Bandwidth (3.1 kHz)
The human voice can produce sounds up to 20 kHz,
but most sound is between 300 Hz and 3.4 kHz.
The bandpass filter only passes this sound to reduce bandwidth.
20 kHz