ME 4447/6405
Interrupts and Resets
Suzanne Price
Scott Gilliliand
Greg Graf
Overview
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Polling
Interrupts
Vector Tables
Highest Priority Interrupt Register
ADC Example with Interrupts
Resets
Standby Modes
Suzanne Price
Waiting for an Event : Polling
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WATCH
Program can “poll” for a value to change
We saw this in our ADC lab:
LDAA
ANDA
BNE
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Suzanne Price
ATDSTAT1
#$80
WATCH
;Load the ADC register
;Get only the conversion complete flag
;Loop if conversion is not complete
Prevents processor from running other code

We could not easily control LED’s while checking
the ATDC.
Waiting for an Event: Interrupts
Suzanne Price
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User defined section of code that runs
automatically when an event occurs
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Completion Flag
Change in Pin Voltage
Errors
Others
Suspends main program execution while
interrupt is serviced
Can happen at any time (when enabled)
Maskable and Non-Maskable Interrupts
How Interrupts Work: Review
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Event occurs
Current instruction finishes
If interrupts are enabled:
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Suzanne Price
Push registers to stack
Set interrupt bit(s) in CCR
Run Interrupt Service Routine (ISR) until RTI
Pull register values back from stack
Main program continues to run
Non-Maskable Interrupts
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6 Non-Maskable Interrupts
Higher Priority than
maskable interrupts
Can interrupt Maskable
Interrupt ISRs
X=1 ONLY disables XIRQ
interrupt (and all other
interrupts are still enabled
when X=1)
Suzanne Price
1. POR of RESET
pin
2. Clock monitor
reset
3. COP watchdog
reset
4. Unimplemented
instruction trap
5. Software
interrupt (SWI)
6. XIRQ interrupt
Non-Maskable Interrupts
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At Reset or during Non-Maskable interrupt
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X=1 and I=1
Interrupts cannot be serviced
Clear X bit
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Suzanne Price
TAP instruction
ANDCC #$40 instruction
Software cannot set X bit once cleared unless
non-maskable interrupt occurs
RTI restores X and I bits to pre-interrupt
state
Non-Maskable Interrupts
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XIRQ
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Externally triggered
PE0 pin low = XIRQ interrupt
SWI
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Suzanne Price
Allows an interrupt without an event
MON12 in use: jumps back to DBug12
Unimplemented Instruction Trap
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CPU is given code with invalid opcode
Generates interrupt request to unimplemented
instruction trap vector
Maskable Interrupts
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27 Maskable Interrupts
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Global Masking: controls
execution of all maskable
interrupts (ie. I bit =1, no
maskable interrupts occur)
Local Masking: controls
execution of interrupt on a
peripheral device (ie. ATD)
Suzanne Price
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
IRQ
Real-Time Interrupt
Standard Timer Channel 0
Standard Timer Channel 1
Standard Timer Channel 2
Standard Timer Channel 3
Standard Timer Channel 4
Standard Timer Channel 5
Standard Timer Channel 6
Standard Timer Channel 7
Standard Timer Overflow
Pulse Accumulator A Overflow
Pulse Accumulator Input Edge
SPI transfer Complete
SCI system
ATD
Port J
CRG PLL Lock
CRG Self Clock Mode
Flash
CAN Wakeup
CAN Errors
CAN Receive
CAN Transmit
Port P
PWM Emergency Shutdown
VREG LVI
Maskable Interrupts
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IRQ
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Only external maskable interrupt signal
IRQE bit on IRQCR Register
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Suzanne Price
IRQE=1: Falling Edge Sensitive
IRQE=0: Low Level-Sensitive
Peripheral Subsystems (all other Maskable
Interrupts)
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Flag bit and interrupt enable bit
ATD, Timers, PWM, serial communications, etc.
Highest Priority Interrupt (HPRIO)
Register
Suzanne Price
Address: $001F
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HPRIO register moves one maskable interrupt
to top of priority list
Cannot change priority of non-maskable
interrupts
Procedure to increase priority of maskable
interrupt:
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Set I bit to disable maskable interrupts
Write low byte of interrupt vector to HPRIO
Clear I bit to re-enable maskable interrupts
Highest Priority Interrupt Register
(HPRIO)
Suzanne Price
Address: $001F
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
0
1
1
1
1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
Bit 0
-
PSEL[7:1] – Priority Select Bits
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Selects one interrupts source to be elevated
Can only be written while I-bit in the CCR is set and maskable
interrupts turned off
Write the low byte of the maskable interrupt vector to HPRIO to
elevate that maskable interrupt to the highest priority
Ex: writing $DE to HPRIO elevates the Standard Timer Overflow
to highest priority (Standard Timer Overflow vector = $FFDE)
Interrupt Vector Table
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Interrupt Vector:
stores starting
address of ISR
Interrupt Vector
Table
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List of all interrupt
vectors used by
processor
Stored at $FF00 $FFFF
MON12 and Interrupt Vector Tables
Scott Gilliland
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MON12 stores its own interrupt vectors in $FF00-$FFFF
In order to have an interrupt vector called, it must be
placed in second table, stored in $0F00-$0FFF because
user cannot write to EEPROM
 This table is found in the CML-12C32 reference
manual that came with the board
The MON12 Interrupt Table showing both the actual Vector Table
addresses, and the Ram Vector Table addresses
MON12 and Interrupt Vector Tables
Scott Gilliland
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On an interrupt under
MON12:
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The microcontroller calls the
ISR in the $FFxx range
MON12’s calls the ISR
specified by the user in the
$0Fxx range
The user’s ISR is run from the
address specified in $0Fxx
To the user, it appears that
the Interrupt Vector Table
has moved to $0F00-$0FFF
ADC Interrupt Example : ISR
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Scott Gilliland
Write an Interrupt Service Routine to be run
whenever an ADC interrupt occurs
ISR stores latest value in memory for later
use
Ensure that Sequence Complete Flag is
cleared
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Needed to allow the next interrupt to happen
Write $80 to ATDSTAT0 to clear flag
ADC Interrupt Example : ISR
Scott Gilliland
*Interrupt Service
Routine
Define a starting address
ORG $2000
LDAA ATDSTAT0 Read Status register
Read Result register
LDAA ATDDR0H
Store Value to a reserved memory location
STAA LSTCONV
LDAA #$80
STAA ATDSTAT0
RTI
Reset SFC flag by writing a ‘1’ to it
Ensures that we will get the next interrupt
Finally, call RTI to return from the ISR and
pull register values back from the stack
ADC Interrupt Example: Setup
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Set up Interrupt Vector Table for the ADC
Interrupt
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Needs to be the address of the first instruction of
the ISR
Set up ADC
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Scott Gilliland
Including ASCIE bit to enable ADC interrupts
Enable global maskable interrupts
Processor is now free to run other code
Print the value stored into memory by the ISR
ADC Interrupt Example: Setup
Set I bit to make Interrupt Vector Table
changes safe
Store the address of our ISR ($2000) to the
Interrupt Vector for the ADC ($0FD2)
ORG
SEI
LDX
STX
$1000
LDAA
STAA
LDAA
STAA
#%10000010
ATDCTL2
#%10000101
ATDCTL4
#$2000
$0FD2
LDY #41
DELAY1 DEY
BNE DELAY1
CLI
Scott Gilliland
Setup the ADC, including setting the
ASCIE bit to enable local ADC
interrupts
Wait for the ADC to fully power up,
and then clear the I-bit to enable
all maskable interrupts
ADC Interrupt Example: Full Code
Scott Gilliland
ATDCTL2 EQU
ATDCTL4
ATDCTL5
ATDDR0H
LSTCONV
OUTSTRG
ATDSTAT0
$0082
EQU
EQU
EQU
EQU
EQU
EQU
ORG
STRING1
V1
RMB
FCC
V2
RMB
FCC
FCB
$802
FCC
1
"."
1
" Volts"
$0A,$0D,$04
ORG
SEI
LDX
STX
LDAA
STAA
LDAA
00101
STAA
LDY
DELAY1
BNE
$0084
Define
Constants
$0085
$0090
(ex: ATDCTL4)
$800
$FF5E
$0086
"The voltage is "
Define Strings
and
reserve memory
$1000
#$2000
$0FD2
#%10000010
ATDCTL2
#%10000101
*Start of ISR
*ATD Service Routine Vector
*ADPU = 1, ASCIE=1, ASCIF=0
Setup ADC and
*SRES8=1, Prescaler bits =
ADC
Interrupt
ATDCTL4
#41
DEY
DELAY1
*STD Converter Startup Delay
CLI
Loop
*******
*Many other calculations may be performed here
******
Run any other code
LDAA
#$00
LDAB
LDX
IDIV
XGDX
ADDB
STAB
XGDX
LDAA
MUL
LDX
IDIV
XGDX
ADDB
STAB
LSTCONV
#51
#$30
V1
#10
#51
*Load D with LSTCONV
*Load x with #51
*Divides D by X ->D:X
Convert value and
*Stores B print
to v1
to serial
*Load A with 10
*Multiply A and B (low byte of D)
#$30
V2
*Stores B to v2
#%00010000
ATDCTL5
*Scan=0, MULT=1, cc:CA=000
*Start Conversion
LDX #STRING1
JSR OUTSTRG
LDAA
STAA
JMP Loop
*Interrupt Service Routine
ORG
$2000
LDAA
ATDSTAT0
LDAA
ATDDR0H
STAA
LSTCONV
LDAA
STAA
RTI
END
#$80
ATDSTAT0
*Scan=0, MULT=1, cc:CA=000
*Start Conversion
Interrupt Service
Routine
Resets
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Forces MCU to:
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Greg Graf
Assume set of initial conditions
Begin executing instructions at an assigned
starting address
Like interrupts, resets have a vector to define
the starting address of code to be run
Unlike interrupts, they do not return to
original code location
Resets have different vectors to allow
execution of individualized code
Resets: Process Flow
Greg Graf
When a reset is triggered:
 The address from the vector is loaded into
the program counter
 S, X, and I bits are set in the CCR
 MCU hardware is initialized to reset state
 Check for any interrupts that have occurred
Resets: POR, External, Low Power
Greg Graf
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Power on Reset (POR)
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External Reset (RESET)
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Triggered when Vdd is applied
Timing circuit is initialized, and allowed to settle for 4064
cycles
Same vector as POR
Reset pin must be pulled low for a total of 6 cycles
Low Power Reset
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Same vector as POR
Triggered when Vdd drops below acceptable limit
Resets: COP, Clock Monitor
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Computer operating Properly (COP) Reset
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Greg Graf
Protects against software failures (infinite loops, etc)
When enabled (NOCOP bit in CONFIG register), resets
if free-running watchdog timer rolls over $FFFF
Timer rate is set in the OPTION register. System Eclock is divided by 215 and further scaled by 1, 2, or 4
Clock Monitor Reset
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Protects against clock failure
Set by CME control bit
If enabled, system resets if no clock edges are
detected within a set period.
Standby Modes
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Suspends CPU operation until reset or
interrupt occurs
Reduces power consumption
CPU registers are stacked to speed up
recovery into interrupts
Two modes: Wait, Stop
Greg Graf
Standby Modes: WAIT (WAI)
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Suspends CPU Processing
On-chip crystal oscillator remains active
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Greg Graf
Peripherals keep running
Wait mode is exited through IRQ, XIRQ, or
any internally generated interrupts
Standby Modes: Stop (STOP)
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All clocks and peripherals stopped
I/O pin levels remain static
Stop is exited through external interrupts,
edge-triggered IRQ or RESET pin
XIRQ always exits stop mode, but XIRQ
interrupts are only executed if X bit is clear
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Greg Graf
Otherwise, code continues from STOP command
If S-bit in CCR is set, STOP is treated as NOP
References
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ME 4447/6405 Interrupts and Resets Lecture
HCS12 Reference Manuals
Appendix: Full Code
$0082
EQU
EQU
EQU
EQU
EQU
EQU
$0084
$0085
$0090
$800
$FF5E
$0086
ORG
FCC
RMB
FCC
RMB
$802
"The voltage is "
1
"."
1

FCC
FCB
" Volts"
$0A,$0D,$04

ORG
$1000
SEI
LDX
STX
#$2000
$0FD2
LDAA
STAA
LDAA
STAA
#%10000010
ATDCTL2
#%10000101
ATDCTL4
LDY
DEY
BNE
#41
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ATDCTL2 EQU
ATDCTL4
ATDCTL5
ATDDR0H
LSTCONV
OUTSTRG
ATDSTAT0
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STRING1
V1
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V2
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*Start of ISR
*ATD Service Routine Vector
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*ADPU = 1, ASCIE=1, ASCIF=0
*SRES8=1, Prescaler bits = 00101
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DELAY1
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CLI
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*STD Converter Startup Delay
DELAY1
Loop
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*******
*Many other calculations may be performed here
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******
LDAA
LDAB
LDX
IDIV
XGDX
ADDB
STAB
XGDX
#$00
LSTCONV
#51
LDAA
MUL
LDX
IDIV
XGDX
ADDB
STAB
#10
LDAA
STAA
JMP Loop
*Interrupt Service Routine
ORG
LDAA
LDAA
STAA
LDAA
STAA
RTI

End

*Load x with #51
*Divides D by X. Stores remainder to D and the result in X
#$30
V1
*Stores B to v1
*Load A with 10
*Multiply A and B (low byte of Remainder in D)
#51
#$30
V2
*Stores B to v2
LDX #STRING1
JSR OUTSTRG
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*Load D with LSTCONV
#%00010000
ATDCTL5
*Scan=0, MULT=1, cc:CA=000
*Start Conversion
$2000
ATDSTAT0
ATDDR0H
LSTCONV
#$80
ATDSTAT0
*Scan=0, MULT=1, cc:CA=000
*Start Conversion
Interrupt Flow
Interrupt condition
is met
A
B
Global Masking
Analyze Priority
ISR instruction
YES
NO
YES
Local Masking
Set (I) or (X)
to prohibit another
Interrupt
NO
Complete Current
Instruction
Store all registers
on the Stack
Continue
Program
A
Standard Interrupt
Table
Load Address in
appropriate vector
B
NO
RTI
YES
Clear I or X bit in
CCR
Restore Registers
w/ org. Values
Note: Local mask must
be cleared prior to
performing RTI