Tools for Discovery
Digital Pulse Processing
for Physics Applications
PSI - March 15th 2011
Carlo Tintori
Outline
•
Description of the hardware of the waveform digitizers
•
Overview on the CAEN Digitizer family
•
Use of the digitizers for physics applications
•
Comparison between the traditional analog acquisition chains and the new fully
digital approach
•
DPP algorithms:
• Pulse triggering
• Zero suppression
• Pulse Height Analysis
• Charge Integration
• Gamma-Neutron discrimination
• Time measurement
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Digitizers vs Oscilloscopes
• The principle of operation of a waveform digitizer is the same as the
digital oscilloscope: when the trigger occurs, a certain number of
samples is saved into one memory buffer (acquisition window)
• However, there are important differences:
–
–
–
–
no dead-time between triggers (Multi Event Memory)
multi-board synchronization for system scalability
high bandwidth data readout links
on-line data processing (FPGA or DSP)
Memory Buffer
TIME STAMP
S[0]
S[1]
S[2]
S[3]
ACQUISITION WINDOW
S[n-1]
Sampling Clock
TRIGGER
PRE
POST TRIGGER
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Time
Highlights
•
•
•
•
•
•
•
•
•
VME, NIM, PCI Express and Desktop
VME64X, Optical Link (CONET), USB 2.0, PCI
Express Interfaces available
Memory buffer: up to 10MB/ch (max. 1024 events)
Multi-board synchronization and trigger
distribution
Programmable PLL for clock synthesis
Programmable digital I/Os
Analog output with majority or linear sum
FPGA firmware for Digital Pulse Processing
Software for Windows and Linux
• From 2 to 64 channels
• Up to 5 GS/s sampling rate - Up to 14 bit
• FPGA firmware for Digital Pulse Processing
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x720
x721
x731
x751
x761
x740
x742
Bandwidth (MHz)
Memory
(Msample/ch)
DPP firmware
Single Ended /
Differential Input
Input Dynamic
Range (Vpp)
Number of
channels
8
4
N. Bit
Form Factor
x724
VME
Desktop/NIM
Max. Sampling
Frequency (MS/s)
MODEL
Digitizers Table
40
0.5; 4
TF, SG
SE, D
100
14
0,5; 2.25; 10
SE
PCIe
2
SE
VME
8
SE, D
Desktop/NIM
4
PCIe
2
VME
8
VME
8/4
Desktop/NIM
4/2
250
12
2
SE
SE
125
1.25; 10
CI, NG
500
8
2
SE, D
250
2
no
250/500
2/4
no
500
1.8; 14.4 /
3.6; 28.8
no
tbd
7.2; 57.6
no
SE, D
500/1000
8
2
SE
PCIe
2
SE
VME
8/4
SE, D
Desktop/NIM
4/2
VME
2
Desktop/NIM
1
VME
64
Desktop/NIM
32
VME
32+2
Desktop/NIM
16+1
1000/2000
10
1
4000
10
1
65
12
2
SE
30
0.19; 1.5
no
5000
12
1
SE
600
0.128
no
SE
SE, D
SE
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Architecture
DAUGTHER BOARDS
MOTHER BOARD
CLK-OUT
SAMPLING CLOCK
CLK-IN
PLL
FIXED GAIN
AMPLIFIER
ANALOG
INPUTs
INT. OSCILL.
+
ADC
LOCAL BUS
FPGA
(AMC)
DAC
GLOBAL TRG
SYNC
FPGA
(VME)
VME/USB
CONET
SELF TRG
TRG-IN
n CHANNELS
SYNC-IN
SRAM
MEMORY
TRG-OUT
I/Os
DAC
MONITOR
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Digitizers for Physics Applications
• Traditionally, the acquisition chains for radiation detectors are made out
of mainly analog circuits; the A to D conversion is performed at the very
end of the chain
• Nowadays, the availability of very fast and high precision flash ADCs
permits to design acquisition systems in which the A to D conversion
occurs as close as possible to the detector
• The data throughput is extremely high: it is no possible to
transfer row data to the computers and make the analysis offline!
• On-line digital data processing in needed to extract only the information
of interest (Zero Suppression & Digital Pulse Processing)
• The aim of the DPP for Physics Applications is to provide FPGA
algorithms able to make in digital the same functions of analog modules
such as Shaping Amplifiers, Discriminators, Charge ADCs, Peak Sensing
ADCs, TDCs, Scalers, Coincidence Units, etc.
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Traditional chain: example 1
charge sensitive preamplifiers
TIME
Q = ENERGY
DETECTOR
DECAY TIME
RISE TIME
PREAMPLIFIER
PEAK AMPLITUDE = ENERGY
•
•
SHAPING AMPLIFIER
TIMING AMPLIFIER
ZERO CROSSING
CFD
This delay doesn’t depend
on the pulse amplitude
•
Typically used with semiconductor
detectors (Si, Ge)
The preamp. output signal is rather
slow (typ. decay time = 50us)
Very high energy resolution (good
S/N ratio)
CFD OUTPUT
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Traditional chain: example 2
trans-impedance (current sensitive) preamplifier
TIME
Q = ENERGY
•
DETECTOR
ZERO CROSSING
CFD
GATE
•
•
DELAYED SIGNAL
Typ. used with scintillators + PMTs or
SiPMs
The preamplifier is optional (the gain is
already in the PMT)
Fast signals (typ. 10-100ns)
CHARGE
INTEGRATION
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Benefits of the digital approach
• One single board can do the job of several analog modules
• Full information preserved: A/D conversion as early as possible, data
reduction as late as possible
• Reduction in size, cabling, power consumption and cost per channel
• High reliability and reproducibility
• Flexibility (different digital algorithms can be designed and loaded at
any time into the same hardware)
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Standard vs DPP firmware
Standard Firmware:
• raw waveform mode (event = sequence of samples)
• common trigger on all channels simultaneously
• trigger time stamp
• channels self trigger: digital discriminator with absolute threshold
• channel self triggers ORed to make the common trigger
• zero suppression (sole data reduction technique)
DPP Firmware
• on-line dead-timeless data processing
• multi-parametric list mode (event = time stamp, pulse height, charge, etc…)
• combined acquisition mode: list + short waveform for further analysis off-line
• channels can trigger independently
• pulse triggering: baseline restore, smooth filters, rise time discriminator, etc…
• pulse time stamp
• pulse shape analysis (e.g. gamma neutron discrimination)
• individual trigger propagation on channel basis, also from board to board
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Raw waveform mode vs DPP events
STD FW
EVENT DATA
S1
S2
S3
S4
S5
S6
S7
Acquisition Window
Threshold
INPUT
Trigger
Sn
Typ. Nsample > 1K
DPP FW
Leading Edge
EVENT DATA
TRAPEZ
HEIGHT
INPUT
SAMPLES
MEAN
SUM
CHARGE
TIME STAMP
CHARGE
BASELINE
HEIGHT
S1
S2
S3
S4
Typ. Nsample < 100
BASELINE
Threshold
TIMING
FILTER
ZCROSS
TIME STAMP
Trigger
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Coincidence and Event correlation
• When running in list mode, the bandwidth requirement is much lower
than in raw waveform mode.
Example: time stamp + energy = 8 bytes; 8 channels @ 1Mcps = 64 MB/s;
fits the CONET bandwidth.
• General Rule: read all events as long as you have enough bandwidth
(i.e. make data suppression as late as you can)
• Coincidence and anticoincidence applied off-line using the time stamps
• When hardware coincidence is needed, you can:
• Use internal coincidence between the channels of a board to make a
common trigger (STD FW only)
• Use analog sum or majority on the DAC output (only for VME board
with STD FW)
• Use on-line coincidence in the x720+DPP-CI (only between couples
of channels)
• Use GPIOs on the front panel to propagate trigger inputs/outputs
from/to external logic (e.g. V1495)
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Trigger and timing filter (I)
• Pulse triggering is the basis for all DPP and Zero Suppression algorithms
• Fast Shaping filter: digital version of the RC-CRN filter (N=1, 2)
• Immune to baseline fluctuation and low frequency noise (ground loop)
• Pulse identification also with the presence of pile-up
• High frequency noise rejection (RC smoothing filter)
• Can operate as a digital CFD
• Zero crossing for precise timing information
• Off-line interpolation to overcome the sampling period granularity
• Zero crossing of CFD can also be used for rise time discrimination
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Trigger and timing filter (II)
Emulation Mode
CFD
Input
1 BIN = 1.376 KeV
10000
5000
0
-5000
6000
7000
8000
9000
10000
Time (1 sample = 10ns)
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11000
Zero Suppression
• Data reduction algorithms can be developed to reduce the data
throughput:
– Full event suppression: one event (acquisition window) is discarded if no pulse is
detected inside the window
– Zero Length Encoding: only the parts exceeding the threshold (plus a certain
number of samples before and after) are saved.
• The zero suppression is available also with the standard FW (no DPP)
ZLE threshold
suppressed
Look Back
Window
suppressed
Region of
Interest
suppressed
Look Ahead
Window
T
SAMPLES
T
SAMPLES
T
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SAMPLES
DPP-TF
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DPP-TF topics
• Digital implementation of the shaping amplifier + peak sensing ADC
(Multi-Channel Analyzer)
• Charge sensitive preamplifier directly connected to the digitizer
• Implemented in the 14 bit, 100MSps digitizers (mod. 724)
• Use of trapezoidal filters to shape the long tail exponential pulses
• Pile-up rejection, Baseline restoration, ballistic deficit correction
• Low dead time => high counting rate
• Energy and timing information can be combined
• Best suited for high resolution spectroscopy (HPGe and Si detectors)
• Also suitable for homeland security and biomedical applications
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DPP-TF Block Diagram
Thr
a b N
COMP
TRG & TIMING
FILTER
D
RC-(CR)N
ARMED
CLK
TIME STAMP
TRIGGER
COMP
Nsbl
COUNTER
ZERO
N = 1,2
INPUT
DECIMATOR
ftd
kmM
D = 1,2,4,8
SUB
TRAPEZOIDAL
FILTER
Thr = TRG Threshold
Nspk
BASELINE
MEAN
ftd = Flat Top Delay
(ballistic deficit)
K = Shaping Time
PEAK
MEAN
Nspk = Peak mean
M = Time Constant
(PZ cancellation)
b = RiseTime
TIMING
FILTER
TRAPEZOID
zero crossing
Nsbl = Baseline Mean
ENERGY
m = Flat Top
a = Low Pass mean
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Example of trapezoidal filter output
Emulation Mode
Trapezoid
Input
10000
1 BIN = 1.376 KeV
5000
0
Trapezoid Height
= Energy
Pile-up
-5000
-10000
-15000
8000
10000
12000
14000
16000
Time (1 sample = 10ns)
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18000
DPP-TF vs Analog Chain set-ups
N1470
High
Voltage
Ge / Si
N968
N957
Shaping
Amplifier
Peak
Sensing ADC
Energy
C.S.
PRE
DT5724
14bit @ 100MSps
Digitizer + DPP-TF
Energy
Time
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Dead Time in the DPP-TF
•
Unlike the analog chain, in the DPP-TF there is no conversion time
•
The A/D conversion and the pulse processing is always alive; dead time in the
energy filter is only given by the trapezoid overlap (Trise + Tflat)
•
Although pile-up causes the loss of energy values, the timestamps is given
for almost all pulses: true rate can be calculated
•
Double pulse resolution  Rise Time (two pulses separated by at least the rise
time can be distinguished)
•
The rise time discriminator allows double pulses piling up on the rising edge to
be detected and counted twice
•
Residual multiple pulses that cannot be distinguished (despite the RTD) can be
taken into account on a statistical basis
•
Histogram (spectrum) calculated off-line: easy implementation of techniques for
the ‘dead-time’ correction (loss of energy counts)
•
The number and the timing of lost counts is known: they can be dynamically
re-distributed on the histogram. This is very important in the cases where the
activity is not constant in time.
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Individual inter-channel triggering
• Feature developed for the project Prospectus (compton camera)
• Mainly needed in segmented or clove detectors
• One channel triggers itself and also neighbour channels (also from
board to board
• Individual TRG-IN and TRG-OUT lines from each channel to the Front
Panel GPIO connector (8 inputs + 8 outputs)
• External trigger unit (V1495) for the coincidence matrix implementation
• Available in the new DPP-TF (x724 series)
• Can be implemented in the x720 and x751 series as well
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Example of System Integration
SLOW CONTROL
CLOCK
MASTER
BOARD
CLOCK DISTRIB.
Progr. Phase shift
V1718
VME
VME-USB
TRIGGER
SYNC START/STOP
CONET OPTICAL LINK
Readout and/or control
80MB/s, up to 4x8 boards
TRIGGER / SYNC
CONET
TRIGGER
LOGIC
(V1495)
DISCRIM
A3818
PCIe
ANALOG OUT
Thr
ANALOG OUTPUT
Linear Sum,
Majority
One PC can read
up to 32 boards
(256 channels!)
INDIVIDUAL
TRIGGER IN/OUT
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Test Results with HPGe detectors
•
Preliminary tests performed at LNL (Legnaro - Italy) on Nov-2008 and Feb-2009
•
Further tests at Duke University on Jul-2010
•
Last test at University of Palermo (Dep. Of Phisycs) on Jan 2011:
the detector is an Ortec HP-Ge mod. GEM40P4 cooled with an X-cooler (Peltier). The
preamp is an A257P with a time constant of 100s.
•
Source =
60Co
(count rate = 0.8 KHz)
FWHM @ 1.33 MeV:
1.98 KeV
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Test Results with CdTe at high rate (I)
•
Tests executed at University of Palermo on February 2011
•
Detector: CdTe from Amptek with embedded FET integrator
•
Rise Time = 140 ns, Decay Time = 100 s
•
Source =
•
Tested at 70, 200 and 800 KHz with different DPP parameters
109Cd,
X-ray peaks at 22 and 25 KeV
70 KHz
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Test Results with CdTe at high rate (II)
200 KHz
800 KHz
200 KHz
800 KHz
with Rise Time
Discriminator
with Baseline
Hold-off
SUM PEAKS
NO SUM PEAKS
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DPP-CI
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DPP-CI topics
• Digital implementation of the QDC + discriminator and gate generator
• Implemented in the Mod. x720 - 12 bit, 250MS/s and Mod x751 - 10
bit, 1GS/s or 2GS/s (*)
• Self-gating integration; no delay line to fit the pulse within the gate
• Baseline restoration (pedestal cancellation)
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Energy and timing information can be combined
• Typically used for PMT or SiPM/MPPC readout
(*) Implementation in the Mod. x751 will be ready by April 2011
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DPP-CI Block Diagram
INPUT
b = RiseTime
Thr = TRG Threshold
QLSB = TS * VLSB / 50
= 40 fC (Mod 720)
TIMING
FILTER
a = Low Pass mean
W = Gate width
GATE
Nsbl = Baseline mean
CLK
TIME STAMP
COUNTER
a b
DELAYED
INPUT
Thr
D = Delay (Pre-Gate)
COMP
TRG & TIMING
FILTER
TRIGGER
W
MONOSTABLE
INPUT
D
DELAY
GATE
Nsbl
BASELINE
MEAN
SUB
ACCUMULATOR
(INTEGRATOR)
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CHARGE
DPP-CI vs Analog Chain set-up
N1470
High
Voltage
Delay
N108A
QDC
V792N
Charge
TDC
V1190
Time
Splitter
A315
CFD
N842
Dual Timer
N93B
PMT
NaI(Tl)
DT5720
12bit @ 250MSps
Digitizer + DPP-CI
Charge
Time
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DPP-CI: Test Results with NaI+PMT
NaI detector and PMT directly
connected to the QDC or digitizer
Resolution = FWHM * 100 / Mean
DPP-CI
Analog QDC
Energy (MeV)
Res (%)
Res (%)
0.481 (137Cs Compton edge)
9.41  1.18
12.80  0.70
0.662 (137Cs Photopeak)
7.01  0.04
8.17  0.04
1.33 (60Co Photopeak)
5.67  0.03
6.66  0.18
1.17 (60Co Photopeak)
5.46  0.02
5.89 0.13
2.51 (60Co Sum peak)
3.82  0.11
4.10  0.24
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DPP-CI: Test Results with SiPM kit
SP5600
•Threshold scan
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•0.5 ph
•1.5 ph
•2.5 ph
DPP-CI: Test Results with LaBr
•
Project: SLIM.CHECK (detection of illicit radioactive material)
•
Test performed at JRC Ispra by INFN PD (acknowledges: G. Visti)
•
4 detectors: LaBr, NaI(Tl), NE213, 3He, all read by a V1720 with DPP-CI
•
Source
238U
(348 Kg)
NaI
LaBr
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DPP-NG
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DPP-NG topics
• Digital implementation of the E/E analysis (double gate charge
integration)
• Implemented in the Mod. x720 - 12 bit, 250MS/s and Mod x751 - 10 bit,
1GS/s or 2GS/s (*)
• PSD = (QLONG - QSHORT)/ QLONG
• Typically used with organic liquid scintillators (e.g. BC501)
• Dead-timeless acquisition (no conversion time)
• Alternative analysis (not implemented yet) based on the Rise Time
Discrimination technique: T in the Zero Crossing of two CFDs at 25%
and 75%; applied to integrated output (either from C.S. preamp or
digital integrator)
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-n Discrimination Block Diagram (I)
SHORT GATE
LONG GATE
CLK
COMP
TIME STAMP
TIME
COUNTER
TRIGGER
WAVEFORM
Q-FAST
INPUT
SUB
DELAY
ACCUMULATOR
(INTEGRATOR)
Q-SLOW
EVENT BUILDER
TRGthr
OUT
DATA
BASELINE
PreTrigger
BLns
BLthr
GATE1
GATE2
PULSE SHAPE
DISCRIMINATOR
GateWidth1 GateWidth2
PSDthr
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-n Discrimination Block Diagram (II)
Algorithms tested off-line
Not yet implemented in FW
T
CLK
TIME STAMP
TIME
COUNTER
TRGthr
WAVEFORM
INPUT
SUB
DELAY
BASELINE
PULSE SHAPE
DISCRIMINATOR
CFD
DELAY
25% ATTEN
SUB
ZC
T1
75% ATTEN
SUB
ZC
T2
PreTrigger
BLns
BLthr
PSDthr
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EVENT BUILDER
COMP
OUT
DATA
-n Discrimination: test results (I)
Detector: BC501A 5x2 inches,
PMT: Hamamatsu R1250
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-n Discrimination: test results (II)
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-n Discrimination: test results (III)
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-n Discrimination: test results (IV)
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-n Discrimination: test results (V)
5
0
0
4
5
0
4
0
0
3
5
0
3
0
0
2
5
0
2
0
0
1
5
0
1
0
0
5
0
12bit 250MS/s
'
h
i
s
t
o
g
r
a
m
2
d
.
t
x
t
'
0
-
5
0
-
5
0
0
4
5
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4
0
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3
5
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3
0
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2
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2
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1
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0
5
0
5
0
0
5
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1
0
0
1
5
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2
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0
2
5
0
3
0
0
3
5
0
4
0
0
4
5
0
5
0
0
5
0
0
10bit 1GS/s (off-line)
'
h
i
s
t
o
g
r
a
m
2
d
.
t
x
t
'
0
-
5
0
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5
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0
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2
0
0
2
5
0
3
0
0
3
5
0
4
0
0
4
5
0
Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited
-n Discrimination: test results (VI)
E/E (dual gate)
t CFD (25%, 75%)
(off-line)
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Practical example of off-line coincidence
• Detectors: 2 BC501A
• Source: Na22
• 740.000 events acquired in list
mode (energy+time stamp) from
both detectors
• Off-line analysis: search for timestamp coincidence within 50 ns
• Energy spectrum of all events (up)
and after coincidence (down)
• Energy vs Time of Flight 2-D plot
(below)
ALL
25000
20000
15000
10000
5000
0
0
50
100
150
200
250
300
2000
350
400
COINC
1500
1000
500
0
0
50
100
150
200
250
300
350
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400
TIMING
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Conventional TDCs vs Digitizers
• Conventional TDC boards:
V1190: 128 channel, 100 ps Multi-Hit TDC
V1290: 32 channel, 25 ps Multi-Hit TDC
V775: 32 channel, 35 ps Start-Stop TDC
• TDC in a digitizer can't compete in terms of density and cost, but…
• There are cases where the implementation of a TDC in a digitizer is
profitable:
Time measurement (at medium-low resolution) combined with energy or
other parameters
Extremely high timing resolution (better than 10 ps)
Bursts of very close pulses (e.g. Free Electron Lasers)
Signals unsuitable for the conventional Constant Fraction Discriminators
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Algorithms for the Time Measurements
• DPP time stamp LSB equals the sampling period (Resolution = Ts/12);
• Interpolation between samples improves timing resolution
• It is not worth doing on-line interpolation (floating point consumes FPGA
resources and has no significant data size reduction)
• DPP can make on-line digital CFD or LED and save just 2 (or more)
points for the interpolation to be performed off-line
• Big dependence of the resolution on the rise-time and amplitude
of the pulses (V/ T)
High Resolution ZC after
math. Interpolation
S1
INPUT
S2
Time
S3
Timing
Filter
S4 = ZC time stamp
Resolution = Ts / 12
S4
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ZC timing errors
Timing resolution affected by three types of noise:
TSAMPL
–
–
–
ANALOG
SIGNAL
Electronic noise in the analog signal (here ignored)
Quantization error Eq
Interpolation error Ei
SN
Ei
There are 2 different cases:
Rise Time > 5*Ts
TRUE TIME
linear interpolation is good: Ei << Eq
The resolution is proportional to V/T and to
the number of bits of the ADC.
TIME STAMP
zero
Rise Time < 5*Ts
approximation to a straight line is too rough:
Ei is the dominant error (Eq is negligible). Such
a geometric error varies with the position of the
signal respect to the sampling clock giving non
gaussian spectra and other non-physical effects.
The resolution becomes inversely proportional
to the rise time.
MEASURED TIME
Eq
LINEAR
INTERPOLATION
LSBADC
SN-1
Optimum Rise Time = 5*Ts
for any type of digitizer!
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Sampling Clock phase effect (RT<5Ts)
(I)
When rise time < 5*Ts, the interpolation error has a big variation with the phase
between the rising edge and the sampling clock.
DELAYA-B = N*TS
CHA
ERRA
DELAYA-B = (N+0.5)*TS
ERRA
TIMEAB
CHB
DELAYAB = N * Ts:
same clock phase for A and B 
same interpolation error 
ERRA  ERRB 
Error cancellation in calculating TIMEAB
ERRB
CHA
CHB
ERRB
DELAYAB = (N+0.5) * Ts:
rotated clock phase for A and B 
different interpolation error 
ERRA  ERRB 
No error cancellation. ERRA and ERRB
are symmetric: twin peak distribution
= (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA - ERRB )
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Sampling Clock phase effect (RT<5Ts)
9
0
0
8
0
0
7
0
0
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DELAY = N * Ts
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
DELAY = (N + 0.5) * Ts
0
0
2
0
0
4
0
0
6
0
0
8
0
0
1
0
0
0
1
2
0
0
1
4
0
0
1
6
0
0
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(II)
Sampling Clock phase effect (RT<5Ts)
10
Vpp = 100mV
5 ns
RiseTime
10ns
10 ns
15ns
Rise Time RiseTime
15 ns
RiseTime
20ns
20 ns
30 ns
RiseTime
30ns
RiseTime 5ns
Mod720: 12bit 250MSps
Emulation
Std_Dev[ns]
1
0.1
0.01
3
4
5
6
7
8
Delay[ns]
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9
(III)
Preliminary results: Mod724
(14 bit, 100 MS/s)
5*T
StdDev (ns)
DELAY = N * Ts
DELAY = (N + 0.5) * Ts
RiseTime (ns)
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Preliminary results: Mod720
(12 bit, 250 MS/s)
StdDev (ns)
5*T
RiseTime (ns)
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Preliminary results: Mod751
(10 bit, 1 GS/s)
StdDev (ns)
5*T
NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot
RiseTime (ns)
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Mod724 vs Mod720 vs Mod751
StdDev (ns)
Amplitude = 100 mV
RiseTime (ns)
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Mod751 @ 2 GS/s
The cubic interpolation can reduce the gap between best and
worst case as well as increase the resolution for small signals!
StdDev (ns)
DIGITAL SIGNAL (NIM or ECL)
  5 ps !
Amplitude (mV)
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Work in progress
• We are currently making tests with the x742 series (5 GS/s, 12 bit)
• The use of the x742 is the only way to get a high density, low cost
digitizer giving high energy and timing resolution in one single board
• There is no DPP on-line for the moment; however, the need of DPP for
this board is less important because of the dead-time
• Timing calibration (applied off-line) seems effective
• Linear interpolation between two points gave a timing resolution of
about 30 ps
• We are investigating other types of signal interpolations such as cubic (4
points) or best fit curves with a signal template
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Software for Digitizers
Other Application
DPPRunner
WaveDump
CAENDigitizer Library
CAENComm Library
3rd part
driver
V1718 driver
USB driver
P72XX driver
PCIe
A3818 driver
PCIe
PCI
A2818 driver
USB 2.0
USB 2.0
USB 2.0
PCIe
Digitizers
V1718
A3818
VME
A2818
SBC
V2718
Desktop
Digitizers
VME
Digitizers
NIM
Digitizers
CONET2 (Optical Link)
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