Dynamic Data Stability in
Low-power SRAM Design
Mohammad Sharifkhani, Shah M.
Jahinuzzaman and Manoj Sachdev
Electrical & Computer Engineering
University of Waterloo, Waterloo, ON, Canada
Background
VA
3 DC
solutions
Static Criteria for Data
Stability
[Hill, 1968]
Worst Case Static
Noise Source
[Lohstroh, 1983]
[Seevinck, 1986]
Vn
I +
VB
VA
VB
Static Noise Margin
(SNM)
Vn
I +
• Static Noise Margin (SNM) is based on
– static criteria
– worst case static noise
2
SRAM Cell: Non-linear System
• Different sets of eq. for
accessed and nonaccessed modes
 dVB
C dt  I 3  I1

C dVA  I  I
4
2
 dt
VDD
VH
WL
Cdg
M5
VL
BL
VDD
VL
WL
Cg
A
B
Cgs
M6
VH
VSS
– differential equations
– discontinuity of MOS I/V
characteristics: use of
subthreshold operation
for continuity
M4
M3
BL
VSS
• Analysis of non-linear
system by state-space
VH
Cgd
VSS
M1
Cg
VSS
M2
VGND (VL)
Capacitances affected by change in cell
VGND voltage
Leaking transistor in retention mode
VH VB VTp
V V

 H A
 I 3  I op e nVt (1  e nVt )

VB VL VTn
V V
 A L

nVt
(1  e nVt )
 I1  I on e

VA VL VTn
V V
 B L

nVt
nVt
I

I
e
(1

e
)
on
 2
VA VL VTp
V V

 H B
 I  I e nVt (1  e nVt )
op
 4
3
State-space Analysis of Cell
• Non-linear system
– multiple stable or DC points
• region of convergence
– time domain solutions relies on initial conditions
• trajectories
– 2 Uniformly Asymptotic
Stable (UAS) points
– 1 saddle point
x
x
RoC of S0
• No
discontinuity in
state variable V
– finite
admittance of
access transistors
x
x
x
SM
x
x
x
x
RoC of S1
• While non-accessed
VA
S0
DC Solution of Eq.1
x Arbitrary initial
condition in state
space
Time domain
trajectory towards
Stable Point
x
S1
x
x
x
VB
4
Analogy with Saddle
• Shadow of the ball on 2D
state space: trajectory
• 3 stable points
• Final DC solution
depends on initial
location of the ball
Ball
SM
Shadow of the ball:
representing the
state of the cell
S1
SM
S0
VB
VA
5
Data Unstability in SRAM Cell
VA
Trajectory during the access
and non-access time
S0
Taccess
DC Stable point
non-accessed
X
DC Stable point
accessed
DC Curve
accessed
XM
SM
DC Curve
non-accessed
Tnon-access
RoC of S1
S1
RoC of S0
VB
• Data unstablity: state of cell moves away
from the RoC of the original UAS point
determined in non-accessed mode
– occurs if the accessed cell has only one UAS
point that resides out of the original RoC
6
Dynamic Data Stability Criteria
Cell B
Cell A
2-dimensional SS in
hyper-plane t0
v1
v1
S0
S0
Φ0(t)
S0a
RoC of Φ0
in hyper-plane t0
Tr
Φ0(t)
Ta
Tr
RoC of Φ1
in hyper-plane t0
SM
t0
M
A UAS point
SM
Φ1(t)
S1
v2
t
DC transfer functions for an
accessed cell
ΦM(t)
ΦM(t)
S1a
Region of attraction of
periodic solution ΦM(t)
in hyper-plane t0
DC transfer functions for a
non accessed cell
RoC of Φ0
in hyperplane t0
SMa
Ta
RoC of Φ1
in hyperplane t0
The periodic solution of the
system in the corresponding
region of attraction
Φ1(t)
S1
v2
• State of cell never leaves the RoC of original
logic state
– existence of a periodic solution for the PTV-NL cell
within each RoC of UAS point
• Worst case scenario: infinite access
transactions
7
Properties of Trajectories
• The periodic solutions are convergent 
– don’t have to solve the PTV-NL for all initial
conditions (despite being a nonlinear system)
– the solution will attract the trajectory, if exists
– the initial condition should be in the RoC of
periodic solution
• Proof: beyond the scope of this presentation
8
Static Noise Margin using
Dynamic Criteria
220
Ta = 0.5 ns
200
SNMD (mV)
• SNM redefined as
SNMD: same noise
sources, but
dynamic criteria
• In subthreshold
region, lower cell
access time results
in higher SNMD
Ta = 1 ns
180
Ta = 2 ns
160
VH=1.2V VWL=1.2V
140
Conv
(SNM)
120
100
80
0
0.1
0.2
0.3
0.4
0.5
0.6 0.7
0.8
VL (V)
9
Application in Low-power SRAM
• Segmented Virtual Grounding (SVGND)
scheme is proposed
– low-leakage
– low-write power
• higher write NM
– low excess power on non-selected BL
– minor speed trade-off
– four distinct operational modes
1. Retention
2. Read
3. Accessed retention
4. Write
10
Retention Mode
VH
VH
VDD
VSS
M2 WL
VSS
VH
M6
WL M1
A
B
VH
VL
M4
VSS
VH
VDD
VSS
M5
VSS
M3
VL
VSS
BL
BL
• Array is in hibernation
VH – VL = 0.4V
• No multiple VTs!
• Body effect minimizes
leakage
• Potential issue: data
stability
SVG(Nominal
voltage:VL)
– weak drive transistors
11
Simulation & Measurement Results
• Measurement results
– SNM (220mV)
• Sub-threshold
operation (~22pA/Cell)
500.0p
0.4
SNM(V)
• Stability simulation
results
600.0p
Leakage current/cell(A)
– Leakage current
reduces significantly
0.6
700.0p
400.0p
300.0p
0.2
200.0p
100.0p
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Voltage drop over the cell (V)
0.0
1.2
12
Read Mode
VH
VH
VDD
VWL
– SVG becomes VSS
– bitline discharges via
access & driver
transistors
M6
M1
A
VSS
VH
VDD
VWL
M5
B
VH
VA
M4
VSS
M3
VSS
VSS
BL
• Good data stability
M2
VH
BL
• Multiple words/row
• Only selected word
enters this mode
VSS
– voltage across cell ≈ VH
– VB-VA > VH-VL
13
Accessed Retention Mode
• Non-selected words (BLs) on
selected row enters this mode
VH
VH
VDD
VWL
• Minimum access leakage
• Issue: data stability
VSS
M6
A
VH-DV
M4
VSS
VH
VDD
VWL
M5
M1
B
VH
VSS
M3
VSS
BL
– Vwl= VH+Vtha-VΔ
– VΔ> 200mV
– recovery after access
M2
VH
BL
– high VWL
– no SVG variation
– no bitline discharge
SVG(Nominal
voltage:VL)
14
Write Mode
• Low BL voltage swing
– VWR Sufficiently below VH-VΔ
– BL swing, DVBL ≈ 400 mV
VH
VDD
VWL
M2
• Low power consumption
VSS
– Pwrite ∝ VH. DVBL
M6
M1
A
VH-DV
B
VH
M4
VSS
VWR
VDD
VWL
M5
VSS
M3
VL
VSS
BL
– no SVG variation
VH
BL
– VWR= VL
VH
SVG(Nominal
voltage:VL)
15
Segment 0
SVG
SVG0
VL
SSM
SVGM
SS
SVG
CELL
N
VL
– Sharing CVG
SW
SWC
Segment
V VG
switch(SW)
Column
Decoder
L
CVG (High metal layer, nominal
voltage VL excpet for read operation)
VH
Virtual
SVGColumn
Ground (CVG)
WLN
– Connection to CVG
• High metal layer (low cap)
• Nominal VL , read VSS
SVG
VL
SS1
Segment M
• Nominal VL , access Vcvg
• SS / WL : simultaneous
VH
CELL
2
WLN
– Sharing SVG
BL
SVG
WL2
VL
SVG
WL1
CELL
1
Segment 1
WL2
BL
BL
BL
• Constitute the OP modes
• Small area overhead
• Column based
Segment Select 0 (SS0)
SVGND Architecture
WL1
VH
16
READ
SA
Column
Address
SA
Segment
SSi
SA
SS1
WLN
SSM
VL
VL
SVG
WL1
VL
SVG
WL1
CELL
1
SS1
SW
BL
Segment 0
WL2
CELL
2
WLN
CELL
N
VH
VL
SS
Segment VG
switch( SW)
BL
VH
CVG (High metal layer, nominal
voltage VL excpet for read operation)
SVG
SVG0
SVG
Segment Select 0 (SS0 )
Segment
Segment
Segment
VL
SVG
WL1
SWC
SVG
WL2
Segment 1
CVG
SVG
SVG
BL
BL
SVG
Segment
CVG
CVG
BL
Column Virtual
Ground (CVG)
SVG
Segment
Segment
Row
decoder
SVGM
Segment M
CVG
SVG
SVG
BL
Column
Decoder
SVG
CVG
CVG
Post Decoder
BL BL
CVG
Segment
Segment
SS0
SVG
SVG
Row
Address
Post Decoder
Pre-decoder 1
BL
CVG
CVG
Post Decoder
Pre-decoder 2
SVGND Architecture
BL
VH
READ
SA
Column Decoder
READ
M
17
SVGND Architecture
BL
SVG
SVG
SVG
Segment
CVG
CVG
SVG
Segment
BL
Segment
CVG
CVG
SVG
Segment
CVG
SVG
Segment
CVG
Segment
SVG
– Others: ARmode
BL
SS1
Post Decoder
– Only to-be-read
columns
Segment
SVG
Row
Address
Post Decoder
Pre-decoder 1
SVG
Segment
Post Decoder
BL BL
SS0
Pre-decoder 2
Column
Address
CVG
CVG
SSi
CVG
• Post Dec: AND
• No additional HW
for SS
• CVG and BL
voltage variation:
BL
Segment
Row
decoder
READ
Column Decoder
M
SA
SA
18
Comparison: Write
1400
SAC
SVGND
HBLSA
CONV
1200
fJ/Write/bit
1000
800
600
400
200
0
128x4
256x4
512x8
256x8
Size of per bit array (Rows x Columns/wordsize)
512x16
19
Simulated Waveforms
>130mV
400mV
>200mV
WL
QR
QR
Cell Accessed
for Read
QA
QA
Adjacent Cell
on the same row
Read Operation
QW
QW
Cell Accessed
for Write
BLA
BLA
BLW
BLW
BLA
BLA
BLR
BLR
WL
QA
QA
Adjacent Cell
on the same row
Write Operation
20
Silicon Implementation
150um
410um
• Array size: 2048x20bit
• 130nm CMOS
• 4 arrays
Cell
SVG
Switch
– Each 150um x 410um
• 8% area overhead
• Fclk>50MHz
21
SVGND Meas. Results
* only relative energy saving compared
to the conventional scheme is reported
x 10 -11
MIT*, ISSCC’06
4
Write Energy (J/Operation)
• Normalized voltage &
freq.
• Less area overhead
compared to
JSSC’04(11%) and
ISSCC’06(66%) and
JSSC’05(18%)
• Ability to accommodate
Multiple words/row
3.5
Samsung, JSSC’05
3
Fujitsu, JSSC’04
2.5
2
1.5
Conv.
Hitachi*, JSSC’06
1
0.5
13
SVGND
12
11
Ad d r
e ss s
10
i ze (b
its)
9
8 0
50
100
150
si z
Word
200
e (b i
250
ts)
22
300