Introduction to Cadence
Opus
Digital HDL design
Physical Knowledgeable Synthesis
(synthesis and place-and-route)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
PKS and Silicon Ensemble PKS
SE-PKS
PKS
Synthesis, Placement
Clock Tree Generation
Silicon Ensemble
DEF
HDL
Floorplanning
DEF
HDL
Floorplanning
refinement
Post Clock Tree Optimization
Global Routing and Optimization
SI Analysis and Repair
Delay Calculation
DEF
WDB
SPF
Final Routing
Parasitic Extraction
WRoute ECO
DEF
HDL
In-Place Optimization
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Verification
Physical synthesis design flow
Productivity:
RTL/Gate Source
Synthesis
Library
Time-to-market:
Integration of synthesis, placement,
global routing eliminates iterations.
Quality of results:
The PKS engine performs orders of
magnitude more tradeoffs than
possible manually.
Physical
Library
(LEF)
TCL Command Interface
PKS
BuildGates Extreme
Physical Optimization
Placement-driven Scan synth
Cadence Opus
course
Clock Tree Synthesis
Global routing
Postroute opt. & SI repair
Global
Routed
Database
Predictability:
Silicon Ensemble placement and
global routing inside, used by final
router provides superior correlation.
Crosstalk prevention
Final Routing
Parasitic Extraction
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Common Timing Engine (CTE)
Greater than 1 million gate RTL
synthesis and greater than 5 million
gate optimization means even the
largest designs can be done using
a flat methodology.
Timing Constraints Physical Constraints
SPEF
D/RSPF
Silicon Ensemble® PKS
optimization place-and-route
Main features
• Chip-level synthesis  higher quality of results
(QOR) and higher productivity
• Automatic time budgeting
• Automatic architecture selection
• Automatic operator merging
• Full, incremental accurate timing analysis
• Productive design analysis and debug
• Enhanced component library
• Easy to use interface
• One-pass test and clock-tree synthesis
• Inside placement and global routing
• Faster run times and larger design capacity
4
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Chip-level synthesis
• With its high capacity and high performance, the PKS tool
enables chip-level synthesis.
• Chip-level synthesis yields better quality of results (QOR).
– Full path visibility
– Optimal path constraints
– Constant propagation
Block level
Overconstrained—bad area
Underconstrained—bad timing
Chip level
Focus on complete critical path
Optimal timing and area
Cadence Opus
course
Block-level
optimization
Block-level
optimization
Chip-level optimization
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Chip-level synthesis
• Fewer constraints
– Chip-level constraints are easier
to specify than block level.
– I/O timing is well known.
• Greater automation
– Eliminates budgeting iterations.
– Spends CPU cycles rather
than human cycles.
• 1M gate leading-edge graphics
chip, top-down synthesis:
– 12.5 hrs, 2.7 GB
Cadence Opus
course
BuildGates chip-level synthesis
Chip I/O Constraint
a
b
c
d
e
f
g
Versus
Block-level synthesis
a
b
c
d
e
f
g
• Block constraints
• Multiple block synthesis scripts
• Chip assembly script
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Automatic time budgeting
• Automates bottom-up
synthesis
• Enables design methodologies that require a bottomup approach.
• Automatically computes
lower-level constraints
from top constraints.
• Slack allocation is based
on logic compressibility.
• High capacity reduces the
number of partitions.
Cadence Opus
course
Constraint application
a
b
Automatic generation
c
d
e
h
f
i
g
j
k
l
m
n
Block i
Block h
6 ns
block target
10 ns
chip target
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
4 ns
block target
Automatic architecture selection
• On-the-fly component
generation
• Context-driven Operand
width
• constant input influences
architecture
• Timing-driven
– Faster for critical
– Smaller area for offcritical path
a
b
c
+
Z
Ripple
Non-booth
Clk
Ripple
d
Cadence Opus
course
+
*
d
a
b
c
Clk
CLA
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
+
Z
*
Booth
+
CLA
Automatic operator merging
• Merging sum-of-products,
product-of-products, productof-sums
• Relational operators merged
• Automatic carry-save
inferencing
– Applicable to product-of-sum,
multiple fan-out signal, etc
– Takes care of both signed
and unsigned arithmetic
• Integrated with logic synthesis
B
A
C
Carry
Propagate
Adder
Z
A
B C
Faster and smaller implementation !
Cadence Opus
course
D
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Z
D
Full incremental timing analysis
• Only individual gate is retimed.
• Demand-driven algorithm performs only necessary
updates.
D Q
D Q
CLK
CLK
retime
critical path!
stale data okay
unchanged
D Q
CLK
U1
D Q
CLK
• Much larger design capacity and less memory usage.
• Converging synthesis results.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Productive analysis and debug
•Analysis features
–
–
–
–
–
Highlight worst paths, endpoints
Highlight cones of logic
Critical path analysis
Timing histograms
Cross-correlation between
reports and RTL
– Accurate timing displayed on
schematic
•Easy design exploration
– Design hierarchy viewer
– Interactive cell swap with
incremental retime
•Ease of customization
– TCL shell command window
– HTML-based help
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Enhanced component library
• All library components are generated on the fly.
• Nearly hand-crafted quality components.
• Additional High-Quality Components
– N-stage pipelined multiplier
– Multiply-accumulate
– Vector adder
– Comparators
– Generalized sum of products
– Rounding
– Programmable incrementer
/decrementer
Cadence Opus
course
– Programmable adder
/subtractor
– Divider
– Shift registers
– Rotate left/right
– Universal multiplexer
– Overflow detection
– …. Many more….
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Easy to use
• PKS Synthesis is easy to use and has the following
advantages:
– Has an easy to use graphical interface.
– Uses the easy to learn Tcl language and extensions.
– Allows running batch scripts.
– Uses an intuitive constraint manager.
– Allows interrupt-reconstrain-restart synthesis.
– Has comprehensive reports.
13
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
One-pass test synthesis
•
•
•
•
•
•
•
•
•
•
•
Top-down and bottom-up scan insertion
Verilog/VHDL (RTL and/or structural netlists)
Multiple clock domains (on separate chains)
Multiple balanced scan chains
Scan/Nonscan register reporting
Single-pass test synthesis
Full register scan
Multiple scan styles
DFT rule checking
Test mode setup
Shared I/O for test pins
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Physical hierarchy in PKS
• Hierarchical optimization
enabled by:
– Read hierarchical floorplan
– Cluster creation and import
(PDEF 3.0)
– Soft blocks or regions
– Push/pull of floorplan
information
– Timing model extraction
– Hierarchical Steiner routing
and stitching
– Block growing enhancements
Cadence Opus
course
Floorplanner
(First Encounter,
ASIC vendor, etc.)
RTL/Gate Source
Constraints
Hierarchical
Floorplan
PKS
Hierarchical Optimization
and Timing Closure
Place & Route
(Routing, extraction, etc.)
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
True global routing
• Router models congestion
exactly.
–
–
–
–
Resource availability
Placement and routing obstructions
Preplaced cells, fillers, spare cells
Prerouted power, clock spines
Example
• 10 paths to route
• 7 paths are timing critical
• 5 paths through congested area
• Router models detailed hardblock routing obstructions.
– Routes over complex hard-block
obstructions.
– Routes to internal hard-block pins.
Cadence Opus
course
• Which paths will be detoured?
• Will detoured paths be re-optimized?
• Will P&R detour the same paths?
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
The PKS solution: RTL to GDSII
• Gives immediate feedback on RTL
• Provides RTL designers the physical timing results
after synthesis
• Achieves one-pass timing closure
• Uses placement and global routing to calculate
interconnect delays
• Brings physical information forward into synthesis
• Produces a placement and global routed database to
be forward-annotated into P&R
• Makes post-final route optimization
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Available Documentation
• Documentation is available in HTML and PDF formats.
– Includes the complete documentation set (User Guides, Command Reference
and Application Notes). Netscape is shipped with all Cadence synthesis tools
• Subscribe to http://sourcelink.cadence.com for best online
help with Cadence tools.
• There is a text help feature for pks_shell. At the pks_shell
prompt, enter:
help <command_name> or help <error_code>
• Start the GUI with -cdsdocd on to access the online
documentation. (CDSD must be installed)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Prerequisites to start PKS
• Set the Unix environment variables (This solution is site specific!)
setenv CDS_INST_DIR /soft/opus/spr40
setenv CDS_INSTALL_DIR /soft/opus/spr40
setenv PATH $CDS_INST_DIR/tools/bin:$CDS_INST_DIR/tools/dfII/bin:
$CDS_INST_DIR/BuildGates/v04.00-s015/bin:$PATH
setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATH
• Set Cadence license environment variable
setenv CDS_LIC_FILE license_file
• Check the special licenses!
ENVISIA_PKS
ENVISIA_SE_SI_place_route
ENVISIA_Utility
Clock_Tree_Generation
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Getting Started with synthesis
In the next few pages, you will become familiar with the
basic commands and acronyms needed to perform a
simple synthesis run. The case studies that follows lets
you experiment with the software.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
PKS synthesis flow
•
•
•
•
•
•
•
•
•
Read the technology library
Parse or read the Verilog or VHDL files
Build a control data flow graph (CDFG)
Build a netlist of generic gates from the CDFG
Define the timing constraints
Check the constraints and netlist
Optimize the generic netlist to a target technology
Analyze the design and verify timing goals
Write out files for place and route and backannotation
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Login into the workstation
Login: cadence
Password: cadence
Guest user
with full rights
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Start up Ambit PKS
Middle click at an empty place
of the screen and the
Engineering Tools popup
window opens.
Make a left click on the
OPUS  Envisia PKS
This solution is site specific!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Start up Ambit PKS
Click on the OK
The PKS graphical user
interface opens.
main window browser
command shell window
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Ambit Database File (ADB)
The ambit database file is used to snapshot the design
project into a database file.
The next time to open an existing design, the .adb file can
be loaded so that no previous command needs to be repeat.
Timing Library File (ALF, TLF, CTLF)
The ALF, TLF or CTLF file is a timing library for the standard
cells. A timing library includes all of the timing information
associated with a particular manufacturing process. Only a
single timing library is required by the SP&R flow, but it is
possible to use a mixture of timing libraries.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Standard Delay File (SDF)
After a generic netlist is generated, Standard Delay Format
(SDF) data can also be loaded to include physical design
constraints. In addition, timing information is conventionally
stored in a SDF file. Individual net RC and design SDF
timing information is annotated to the design within the
synthesis software to provide an accurate timing and design
rule violation view of the design.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the technology library
Left click on the
File  Open...
Select the correct Ambit library/Timing library from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the Verilog/VHDL files
Read in the source Verilog/VHDL files from the path.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Build the generic structure
Left click on the Commands  Build Generic...
Leave the settings
default and click on
OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
View the generic structure
Click on the Modules tab on the center-left window
Any of the modules can be opened with left double-click
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Define ideal clock
Click on the Constraints tab on the
center-right window
Right click on the Constraints tab
window and select New Ideal Clock
Enter master in the name and
10.0 in the period field
Click OK
Click on the Trail Time
and enter 5.0
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Bind clock port to ideal clock
Right click in the right half of the Constraints window under the
Clock Pin and select
New Port Clock
Set master as the Ideal clock
Set clock as the Port clock
Set the early rise time to 0.1 (ns)
Set the early fall time to 5.2 (ns)
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Check the worst path delay
Click on the Schematic tab on the center-right window
Use the right mouse button
to bring up the menu.
Select Worst Path
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Set the target technology
Left click on the Commands  Set Target Technology...
Select the correct technology
Click on OK
Left click on the Commands  Set Operating Parameter…
Select the correct
Voltage
Process
Temperature
Click on OK
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Optimize to a target technology
Click on the Modules tab on
the center-left window
Right click on the top module;
bring up menu and select
Set Current Module
Right click on the top module
again and select
Set Top Timing Module
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Optimize to a target technology
Left click on the Commands  Optimize…
Leave the settings default
and click on OK
If the technology library enables
switch on Minimize Area
Time Budget
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Optimization flow and commands
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Analyze the design
Left click on the Reports  Timing…
Choose the required settings and click on the first icon
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Analyze the design
2 ns
2.7 ns
Leading edge
Clock signal
Tperiod = 4.7 ns
2.3 ns
Early
(Setup time)
Ia
2.3 ns
Late
(Hold time)
Ib
0.05 ns
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Trailing edge
Analyze the design
Left click on the Reports  Area…
Choose the required settings and click on the first icon
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Check the worst path delay
Click on the Schematic tab on the center-right window
Right click on the
Schematic window;
bring up the menu.
Select Worst Path
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Check the slack path histogram
Left click on the Reports  Path Histogram
Choose the required settings and click on the first icon
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Highlight the fanout cone
Right click on one of the gates; bring up the menu
Select Fanout Cone
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Write out files
Left click on the
File  Save
Save ADB database file to the correct path
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Write out files
Click on the shell command window
Write out the generated verilog RTL file by the command
write_verilog -hier cpu_rtl.v
Write out the calculated delays by the command
write_sdf -delimiter . -precision 4 cpu.sdf
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Break!
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study I
Arithmetical Logical Unit (ALU)
The center core of a central processing unit, performs a set
of arithmetic and logic micro operations
Generate a behavior Verilog description of ALU
Sel[4:0]
Sel[1:0]
A[7:0]
B[7:0]
Sel[2]
Logic
Unit
Logic Unit [7:0]
MUX
ALU_noShift[7:0]
Arith Unit [7:0]
Carryin
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Sel[4:3]
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Shifter
Case study I
Arithmetical Logical Unit (ALU)
It has n encoded inputs for selecting which operation to perform
S4
0
0
0
0
0
0
0
0
S3
0
0
0
0
0
0
0
0
S2
0
0
0
0
0
0
0
0
S1
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Cadence Opus
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Operation
Y <= A
Y <= A + 1
Y <= A + B
Y <= A +B + 1
Y <= A + Bbar
Y <= A + Bbar + 1
Y <= A - 1
Y <= A
Function
Transfer A
Increment A
Addition
Add with carry
A plus 1's complement of B
Subtraction
Decrement A
Transfer A
0
0
0
0
Y <= A and B
Y <= A or B
Y <= A xor B
Y <= Abar
AND
OR
XOR
Complement A
Logic Unit
Logic Unit
Logic Unit
Logic Unit
0
0
0
0
Y <= A
Y <= shl A
Y <= shr A
Y <= 0
Transfer A
Shift left A
Shift right A
Transfer 0's
Shifter Unit
Shifter Unit
Shifter Unit
Shifter Unit
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Implementation block
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Arithmetic Unit
Case study I
You can find the verilog sources in the lab1 directory. The
technology and timing library are in the lib directory under
your PKS home directory.
In this exercise you have to do these steps:
•
•
•
•
•
•
•
Load database (.alf and .v) files
Build generic netlist (or use pks_generic.tcl script)
Set the constraints (or use pks_constraints.tcl script)
Optimize the design
Check worst path, timings, area, fan-in and fan-out…
Generate reports into the reports directory
Write out files (.adb, .sdf, rtl_verilog, …)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
Central Processor Unit (CPU)
The design of a processor is a complex scenario. Multimillion
instruction processors (MIPS), complex instruction set
processors (CISC), reduced instruction set processors (RISC)
are all models that are used in different applications.
The HDL description you will be working with is a simple
processor that does 4 simple mathematical functions.
The circuit implements addition, incrementing, complementing
and XOR.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The schematic of CPU
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case Study II
The operation of the CPU
The CPU begins to operate on the positive edge of the reset.
At all positive edge of the clock signal the operation state of the
CPU changes. There are 8 states of the operation / cycle period
On reset signal the counter of the CPU resets, and set pcout
(address of instructions) to 00h – this is the address of the first
instruction. The value of the PC register is incremented per each
cycle
The ALU executes an instruction (which one is determined by
opcode) when ena is enabled.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study II
You can find the verilog sources in the lab2 directory. The
technology and timing library are in the lib directory under
your PKS home directory.
In this exercise you have to do these steps:
•
•
•
•
•
•
•
Load database (.alf and .v) files
Build generic netlist (or use pks_generic.tcl script)
Set the constraints (or use pks_constraints.tcl script)
Optimize the design
Check worst path, timings, area, fan-in and fan-out…
Generate reports into the reports directory
Write out files (.adb, .sdf, rtl_verilog, …)
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Break!
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Getting Started with place-and-route
In the next few pages, you will become familiar with the
basic commands and acronyms needed to generate a
simple layout. The case study that follows lets you
experiment with the software.
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
PKS Place-and-Route Flow
•
•
•
•
•
•
•
•
•
Read the technology library
Read the physical library file
Read the ADB database file
Initialize the floorplan area
Place standard cells and macros
Generate the clock tree
Verify timing goals have been met
Generate and optimize routing
Write out files for backannotation
Cadence Opus
course
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Timing Library File (ALF, TLF, CTLF)
The ALF, TLF or CTLF file is a timing library for the standard
cells. A timing library includes all of the timing information
associated with a particular manufacturing process. Only a
single timing library is required by the SP&R flow, but it is
possible to use a mixture of timing libraries.
Physical Library File (LEF)
A Library Exchange Format (LEF) file is an ASCII file that
contains library information for a class of designs:
•Library data in ASCII format
•Wire unit parasitic information
•Detailed cell size and pin location
•Routing level information
•Macro cell definitions
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Library files
Physical Design Exchange Library File (DEF and PDEF)
The DEF file contains physical design data such as placement
and bounding box data, routing grids, power grids, pre-routes
and rows. DEF can also include additional information such as
routing grids, power grids, pre-routes, and rows. This physical
data is an optional input that would typically be available if this
were a redesign of an existing device.
If the initial DEF file is not available, then an initial floorplan
can be performed in PKS using the set_floorplan_parameters.
This command has many options that can be set. It is also
possible to assign input pins to the left side of the die and
output pins to right side of die or to any other combinations.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the technology library
Left click on the
File  Open...
Select the correct Ambit library/Timing library from the path.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the physical library
Click on the PKS tab in the center-right window
Left click on the the first PKS menu icon
Select the correct Library exchange file from the path.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the ADB database
Left click on the
File  Open...
Select the correct ADB database from the path.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Read the constraints from TCL file
Left click on the
File  Open...
Select the correct TCL source script file from the path.
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Initialize the floorplan
Click on the PKS tab in the center-right window
Right click on the PKS window and select
Define Floorplan
If physical library enables
switch on Abut row pairs
and Flip alternate row
Click on OK
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Initialize the floorplan
Right click in the window under the PKS tab.
Select Port Placement..
Set the Side to be either
top, bottom, left or right by
right click on the side
column. The Index value
of each ports regenerates
automatically
Click on Close
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generated floorplan view
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place standard cells
Right click in the window under the PKS tab.
Select Place cluster…
Switch Timing driven and Congestion driven on if
technology library enables it
Click on OK
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Placed floorplan view
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Department of Electron Devices, CAD Laboratory
Highlight module parts
Click on the Modules tab in the center-left window
Right click on any of the modules; bring up the menu
Select Highlight Physical Instance
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Highlight instance airlines
Middle click on any of the instances on the PKS tab in the
center-right window
Right click on the one of the selected instance name on the Cluster
tab in the center-left window and select Selection Airline
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Highlight Steiner tree
Middle click on any of the instances on the PKS tab in the
center-right window
Right click on the one of the selected instance name on the Cluster
tab in the center-left window and select Selection Airline
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generate clock tree
Enter on the shell command window in the bottom:
set_global instance_generator "ctpks_%d“
set_global net_generator "ctpks_net_CLK_%d"
set_clock_tree_constraints -pin [find –port clock] -min_delay 2.0
-max_delay 2.5 –max_skew 0.3 -max_leaf_transition 1.0
do_uniquely_instantiate
set_clock_root -clock master clock
do_build_clock_tree -noplace -pin [find -port clock]
Generate timing reports
report_clock_tree -pin [find -port clock]
report_clock_tree_violations -pin [find -port clock]
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generate clock tree
Click on the Modules tab in the center-left window
Double click on the top module (cpu)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Place clock tree
Enter on the shell command window in the bottom:
do_place -eco
Click on the Cluster tab in the
center-left window
Right click on the window
and select Select by Name…
and enter ctpks_* to the
Selection Entry field
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Optimize clock tree
Enter on the shell command window in the bottom:
do_xform_optimize_slack –pks
do_xform_ipo
Click on the Cluster tab in the
center-left window
Right click on the window; select
Select by Name… and enter
ctpks_* to the Selection Entry
field
do
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generate global routing
Enter on the shell command window in the bottom:
do_route -timing_driven
Click on the PKS tab
in the center-right
window
Right click on the PKS
window and select
Routing Congestion..
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Optimize global routing
Enter on the shell command window in the bottom:
do_xform_ipo
do_route -timing_driven {do_route -output_db_name cpu_groute.wdb}
Generate report
report_timing -nworst 1 -max_points 10
Check the critical
slack times (must
be positive) !
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Write out files
Click on the shell command window
Write out the generated verilog RTL file by the command
write_verilog -hier cpu_ctpks_rtl.v
Write out the ambit database file by the command
write_adb cpu_ctpks.adb
Write out the physical description file by the command
write_def cpu_ctpks.def
Write out the calculated delays by the command
write_sdf -delimiter . -precision 4 cpu_ctpks.sdf
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Coffee break
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Advanced synthesis tools
In the next few pages, you will become familiar with the
test and data-path synthesis. The case studies that
follows lets you experiment with the software.
Cadence Opus
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Test synthesis overview
• Provides the capability of detecting manufacturing defects in
sequential circuits
• Serialize input test vectors and expected output patterns
through shift register(s)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
PKS test synthesis flow
•
•
•
•
•
•
•
•
•
•
•
Read the technology library
Parse or read the Verilog or VHDL files
Build a control data flow graph (CDFG)
Build a netlist of generic gates from the CDFG
Define the timing constraints
Check the constraints and netlist
Generate scan path(s)
Optimize the generic netlist to a target technology
Display scan path(s)
Analyze the design and verify timing goals
Write out files for place and route and backannotation
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Scan path generation flow
RTL
MBIST,
Test
Boundary Scan,
TAP Controller
Circuit Insertion
Scan or
nonscan gates
RTL+ Test Circuit
Scan DEF file
BuildGates
Order file
ATPG
I/F File
Scan inserted,
gate-level netlist
Silicon Ensemble
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Department of Electron Devices, CAD Laboratory
Scan path styles
Multiplexed flip-flop style
Clocked scan style
Clocked LSDD style
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Department of Electron Devices, CAD Laboratory
Scan path example
Circuit without scan path
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Department of Electron Devices, CAD Laboratory
Scan path example
Circuit with scan path
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Generate scan path(s)
After building generic click on the shell command window
and write the followings
Define the name and logical level of the scan mode selection port
set_scan_mode scan_enable 1
Generate scan path reports (Must do these reports! )
report_dft_assertions
//report existing assertions at this point
check_dft_rules
report_dft_registers
//report details of chainable registers
Define the scan path styles (depends on the technology library)
set_scan_style {muxscan | clocked_scan | clocked_lsdd}
set_test_scan_clock clock
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Department of Electron Devices, CAD Laboratory
Generate scan path(s)
Define the name of the scan_in and the scan_out ports
set_scan_data -clock clock test_in test_out
Define some global environment variables
set_global dft_scan_avoid_control_buffering true
set_global dft_scan_path_connect chain
Define the number (= 4) and length (= 100) of the paths
set_max_scan_chain_length 100
set_number_of_scan_chains 4
Optimize the design
do_optimize
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Department of Electron Devices, CAD Laboratory
Display Scan path(s)
In the command window type command display_scan_chains
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Department of Electron Devices, CAD Laboratory
Datapath synthesis overview
After reading in the RTL code,
datapath synthesis identifies all
of the datapath operators in the
design, and partitions the
datapath portions from the
control logic.
Datapath synthesis looks at how
the (datapath and non-datapath)
operators interact with each
other in the design, and
identifies all datapath partitions.
Control path,
basic datapath
Verilog/VHDL
Control
Datapath synthesis makes each
partition as large as possible, so
long as there are no nondatapath operators in any
datapath
partition.Budapest University of Technology & Economy
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Datapath
* *
+ -
BuildGates
Extreme or
PKS
Design
implementation
Place and route
PKS datapath synthesis flow
•
•
•
•
•
•
•
•
•
•
Read the technology library
Parse or read the Verilog or VHDL files
Set datapath global environment variables
Build a control data flow graph (CDFG)
Build a netlist of generic gates from the CDFG
Define the timing constraints
Check the constraints and netlist
Optimize the generic netlist to a target technology
Analyze the design and verify timing goals
Write out files for place and route and backannotation
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Datapath synthesis
Before building generic netlist click on the shell command
window and set the followings global environment variables
Switch on datapath synthesis
set_global aware_implementation_selection true
Select the adder architecture
set_global aware_adder_architecture {fcla|csel|cla|csum|ripple}
fcla
csel
cla
csum
ripple
– Fast carry look ahead adder (highest speed; largest area)
– Carry select adder (higher speed; large area)
– Carry look ahead adder (high speed; medium area)
– Conditional sum adder (medium speed; small area)
– Ripple carry adder (low speed; smallest area)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Datapath synthesis
Select the multiplier architecture
set_global aware_multiplier_architecture {booth|non_booth}
booth
non-booth
– Booth-encoded multiplier
– Regular multiplier
Select the architecture style
set_global aware_merge_operator {false|true}
set_global aware_carrysave_inferencing {true|false}
Create generic netlist
do_build_generic
Load the constraints and generate reports
report_resources -hier
Optimize the design
do_optimize {-restructure_aware}
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Department of Electron Devices, CAD Laboratory
Datapath synthesis
There is one synthesis directive that affects architecture of
individual arithmetic operators:
// ambit synthesis key_command { = “ list of parameters “ } ;
Examples
assign y = a * /* ambit synthesis architecture = “booth,cla” */ b +c;
assign y= a * b // ambit synthesis merge_boundary;
assign y= a + b // ambit synthesis architecture = “ripple”;
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Break!
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study III (CPU)
You can find the verilog sources in the lab3 directory. The
technology and timing library are in the lib directory under
your PKS home directory.
In this exercise you have to do these steps:
• Load the technology library and recently saved database
(.alf, .lef, .adb)
• Load and run the pks_constraints.tcl to set the constraints
• Generate floorplan
• Place standard cells
• Generate reports, check slack times, area, …
• Generate clock_tree
• Optimize clock_tree
• Generate global route
• Write outputs (.adb, .def, .sdf, .gcf, .wdb, new verilog RTL)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study IV (CPU)
You can find the verilog sources in the lab4 directory. The
technology and timing library are in the lib directory under
your PKS home directory.
In this exercise you have to do these steps:
•
•
•
•
•
•
•
•
•
Load database (.alf and .v) files
Set datapath global environment variables
Build generic netlist (or use pks_generic.tcl script)
Set the constraints (or use pks_constraints.tcl script)
Generate scan path(s)
Optimize the design
Display scan path(s)
Generate datapath and timing reports
Write out files (.adb, .sdf, rtl_verilog, …)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Full Break!
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory