CMOS Factory
ROCHESTER INSTITUTE OF TECHNOLOGY
MICROELECTRONIC ENGINEERING
CMOS Factory Laboratory
Dr. Lynn Fuller
Webpage: http://people.rit.edu/lffeee
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Fax (585) 475-5041
Email: Lynn.Fuller@rit.edu
MicroE Webpage: www.microe.rit.edu
Rochester Institute of Technology
Microelectronic Engineering
1-20-2015
© January 20, 2015, Dr. Lynn Fuller, Professor
CMOS_Factory.ppt
Page 1
CMOS Factory
INTRODUCTION
This document contains items that should be included in the
students lab notebook. This includes general information about the
processes and products made in the student factory.
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 2
CMOS Factory
INTRODUCTION
RIT is supporting two different CMOS process technologies. The
older p-well CMOS and SMFL-CMOS have been phased out. The
SUB-CMOS process is used for standard 3 Volt Digital and Analog
integrated circuits. This is the technology of choice for teaching
circuit design and fabricating CMOS circuits at RIT. The ADVCMOS process is intended to introduce our students to process
technology that is close to industry state-of-the-art. This process is
used to build test structures and develop new technologies at RIT.
RIT p-well CMOS
RIT SMFL-CMOS
RIT Subµ-CMOS
RIT Advanced-CMOS
l = 4 µm
l = 1 µm
l = 0.5 µm
l = 0.25 µm
Lmin = 8 µm
Lmin = 2 µm
Lmin = 1.0 µm
Lmin = 0.5 µm
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 3
CMOS Factory
RIT SUBµ CMOS
RIT Subµ CMOS
150 mm wafers
Nsub = 1E15 cm-3
Nn-well = 3E16 cm-3
Xj = 2.5 µm
Np-well = 1E16 cm-3
Xj = 3.0 µm
LOCOS
Field Ox = 6000 Å
Xox = 150 Å
Lmin= 1.0 µm
LDD/Side Wall Spacers
2 Layers Aluminum
Rochester Institute of Technology
Microelectronic Engineering
L
Long
Channel
Behavior
3 Volt Technology
VT’s = +/- 0.75 Volt
Robust Process (always works)
Fully Characterized (SPICE)
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 4
CMOS Factory
RIT SUBµ CMOS
NMOSFET
N+ Poly
PMOSFET
0.75 µm Aluminum
6000 Å
Field Oxide
p+ well
contact
N+ D/S
LDD P+ D/S
LDD
P-well
N-well
Channel Stop
P-type Substrate 10 ohm-cm
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 5
n+ well
contact
CMOS Factory
SUB-CMOS 150 PROCESS
SUB-CMOS Versions 150
1. CL01
2. OX05--- pad oxide, Tube 4
3. CV02- Si3N4-1500Å
4. PH03 –1- JG nwell
5. ET29 – Nitride Etch
6. IM01 – n-well
7. ET07 – Resist Strip
8. CL01
9. OX04 – well oxide, Tube 1
10. ET19 – Hot Phos Si3N4
11. IM01 – p-well
12. OX06 – well drive, Tube 1
13. ET06 - Oxide Etch
14. CL01
15. OX05 – pad oxide, Tube 4
16. CV02 – Si3N4 -1500 Å
17. PH03 – 2 – JG Active
18. ET29 – Nitride Etch
19. ET07 – Resist Strip
20. PH03 - -Pwell Stop
21. IM01- stop
22. ET07 Resist Strip
23. CL01
24. OX04 – field, Tube 1
25. ET19 – Hot Phos Si3N4
26. ET06 – Oxide Etch
27. OX04 – Kooi, Tube 1
28. IM01 – Blanket Vt
29. PH03 – 4-PMOS Vt Adjust
30. IM01 - Vt
31. ET07 – Resist Strip
32. ET06 – Oxide Etch
33. CL01
34. OX06 – gate, Tube 4
35. CV01 – Poly 5000A
36. IM01 - dope poly
37. OX08 – Anneal, Tube 3
38. DE01 – 4 pt Probe
39. PH03-5-JG poly
40. ET08 – Poly Etch
41. ET07 – Resist Strip
42. PH03 – 6 - n-LDD
43. IM01
44. ET07 – Resist Strip
45. PH03 – 7 - p-LDD
46. IM01
47. ET07 – Resist Strip
48. CL01
49. CV03 –TEOS, 5000A
50. ET10 - Spacer Etch
51. PH03 – 8 - N+D/S
52. IM01 – N+D/S
53. ET07 – Resist Strip
54. PH03 – 9 P+ D/S
55. IM01 – P+ D/S
56. ET07 – Resist Strip
57. CL01 Special - No HF Dip
58. OX08 – DS Anneal, Tube 2
59. CV03 – TEOS, 4000A
60. PH03 – 10 CC
61. ET26 - CC Etch
62. ET07 – Resist Strip
63. CL01 Special - Two HF Dips
64. ME01 – Metal 1 Dep
65. PH03 -11- metal
66. ET15 – plasma Etch Al
67. ET07 Resist Strip
68. SI01 - Sinter
69. CV03 – TEOS- 4000Å
70. PH03 – VIA
71. ET26 – Via Etch
72. ET07 – Resist Strop
73. ME01 – Metal 2 Dep
74. PH03- M2
75. ET15 – plasma Etch Al
76. ET07 - Resist Strip
77. SEM1
78. TE01
79. TE02
80. TE03
81. TE04
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
2-6-13
Page 6
CMOS Factory
ASML 5500/200
NA = 0.48 to 0.60 variable
= 0.35 to 0.85 variable
With Variable Kohler, or
Variable Annular illumination
Resolution = K1 l/NA
= ~ 0.35µm
for NA=0.6,  =0.85
Depth of Focus = k2 l/(NA)2
of Technology
= > 1.0 µmRochester
for Institute
NA
= 0.6
Microelectronic
Engineering
i-Line Stepper l = 365 nm
22 x 27 mm Field Size
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 7
RIT SUB-CMOS PROCESS
NMOSFET
N+ Poly
PMOSFET
LVL 6 – P-LDD
0.75 µm Aluminum
LVL 1 – n-WELL
6000 Å
Field Oxide
p+ well N+ D/S LDD
contact
P-well
N-well
LDDP+ D/S n+ well
contact
LVL 7 – N-LDD
LVL 2 - ACTIVE
Channel Stop
P-type Substrate 10 ohm-cm
LVL 8 - P+ D/S
LVL 3 - STOP
POLY
CC
ACTIVE
P SELECT
LVL 9 - N+ D/S
LVL 4 - PMOS VT
METAL
LVL 10 - CC
LVL 5 - POLY
N SELECT
N-WELL
11 PHOTO
LEVELS
LVL 11 - METAL
CMOS Factory
ASML MASK
Chrome Side
Mirrored 90°
Chip Bottom at Bottom
Rochester Institute of Technology
Microelectronic Engineering
Non Chrome Side
As loaded into Reticle Pod,
Chrome Down, Reticle PreAlignment Stars Sticking out
of Pod
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 9
CMOS Factory
RIT ADVANCED CMOS
RIT Advanced CMOS
150 mm Wafers
Nsub = 1E15 cm-3 or 10 ohm-cm, n or p
Nn-well = 1E17 cm-3
L
Xj = 2.5 µm
Np-well = 1E17 cm-3
Xj = 2.5 µm
Shallow Trench Isolation
Field Ox = 4000 Å
Long
Dual Doped Gate n+ and p+
Channel
Xox = 100 Å
Behavior
Lmin= 0.5 µm
LDD/Nitride Side Wall Spacers
TiSi2 Silicide
Tungsten Plugs, CMP, 2 Layers Aluminum
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 10
CMOS Factory
RIT ADVANCED CMOS
NMOSFET
PMOSFET
N+ Poly
p+ well
contact
P+ Poly
N+ D/S
P+ D/S
LDD
P-well N-well
LDD
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 11
n+ well
contact
CMOS Factory
ADV-CMOS 150 PROCESS
ADV-CMOS Versions 150, Two level Metal
1. OX05--- pad oxide 500 Å, Tube 4 21. PH03 – level 5 - P-well retrograde
22. IM01 – 1E14, B11, 45 KeV
2. CV02- 1500 Å Si3N4 Deposition
23. ET07 – ash
3. PH03 – level 1- STI
24. ET06 – etch 500 Å pad oxide
4. ET29 - etch Nitride
25. CL01 – pre-gate oxide RCA clean
5. ET07 – ash
26. ET06 – etch native oxide
6. CL01 – RCA clean
27. OX06 – 30 Å gate oxide, Tube 4
7. OX04 – First Oxide Tube 1
28. CV01 – poly deposition, 2500 Å
8. ET06 – Etch Oxide
nd
29. PH03 – level 6 - poly gate
9. OX04 – 2 Oxide Tube 1
30. ET08 – poly gate plasma etch
10. ET19 – Etch Nitride
31. ET07 – ash
11. PH03 – level 2 - N-well
31
32. CL01 – RCA clean
12. IM01 – 5E13, P , 170 KeV
33. OX05 – poly re-ox, 250 Å, Tube 4
13. ET07 – ash
34. PH03 – level 7 - p-LDD
14. PH03 – level 3 - P-well
35. IM01 – 9E14, BF2, 20 KeV
15. IM01 – 7E13, B11, 100 KeV
36. ET07 – ash
16. ET07 – ash
37. PH03 – level 8 - n-LDD
17. OX06 – Well Drive, Tube 1
18. PH03 – level 4 - N-well retrograde 38. IM01 – 5E15, P31, 20 KeV
39. ET07 – ash
19. IM01 – 9E13, P31, 70 KeV
40. CL01 – RCA clean
20. ET07 - ash
Rochester Institute of Technology
Microelectronic Engineering
41. CV02 – nitride spacer 2500Å 61. ME01 – Aluminum
42. ET39 – sidewall spacer etch 62. PH03 – level 12-metal
63. ET15 – plasma Al Etch
43. PH03 – level 9 - N+D/S
31
64. ET07 – ash
44. IM01 – 1E15, P , 25 KeV
65. CV03 – TEOS
45. ET07 – ash
66. PH03 – Via
46. PH03 – level 10 - P+ D/S
67. ET26 Via Etch
47. IM01 – 5E15 BF2, 27 KeV
68. ME01 Al Deposition
48. ET07 – ash
69. PH03 – Metal 2
49. CL01 – RCA clean
70. ET07 - Ash
50. OX08 – DS Anneal, RTP
51. ET06 – Silicide pad ox etch 72. SI01 – sinter
52. ME03 – HF dip & Ti Sputter 73. SEM1
74. TE01
53. RT01 – RTP 5 sec, 650C
75. TE02
54. ET11 – Unreacted Ti Etch
76. TE03
55. RT02 – RTP 5 sec, 700C
56. CV03 – TEOS, P-5000, 3000Å 77. TE04
57. PH03 – level 11 - CC
58. ET06 – CC etch
59. ET07 – ash
60. CL01 – RCA clean
L = 0.5 m
VDD = 3.0 V
VTN = 0.75 V
VTP = - 0.75V
© January 20, 2015, Dr. Lynn Fuller, Professor
(Revision 05-02-14)
Page 12
RIT ADVANCED CMOS PROCESS
PMOSFET
P+ Poly
NMOSFET
N+ Poly
p+ well
contact
N+ D/S
P+ D/S
N-well
LDD
P-well
LDD
LVL 1 - STI
LVL 7 - PLDD
LVL 2 - NWell
LVL 8 - NLDD
LVL 3 - Pwell
LVL 9 – N+D/S
n+ well
contact
12 PHOTO
LEVELS
POLY
CC
ACTIVE
P SELECT
METAL
LVL 4 - VTP
LVL 10 – P+D/S
LVL 5 - VTN
LVL 11 - CC
LVL 6 - POLY
LVL 12 – METAL 1
N SELECT
N-WELL
CMOS Factory
MASK ORDER CONTINUED
1
2
3
4
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 14
CMOS Factory
PRODUCTS
New John Galt Test Chip (Sub-CMOS and Adv-CMOS)
Older Obsolete Chips:
Mixed Analog/Digital Test Chip (Sub-CMOS Process)
Test Chip (Advanced CMOS Process)
John Galt Test Chip (Sub-CMOS Process)
4-Bit Microprocessor (Sub-CMOS Process)
Analog to Digital Converter (Sub-CMOS Process)
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 15
CMOS Factory
JOHN GALT CMOS TESTCHIP
2010
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 16
CMOS Factory
FACTORY TEAMS - TUESDAY
Red
Group
1. Srishti
2. Varshini
3.
Orange
Group
1. Chetan
2.
3.
Yellow
Group
1. Vetha
2. Jacob
3.
Green
Group
1. Astha
2. Achuthan
3.
Blue
Group
1. Rakesh
2.
3.
Every two weeks groups shift discipline (to the right). For example the red group does
Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc.
Lithography
Diffusion
Bruce Furnace
AG-RTP
Blue M Oven
Nanospec
Spectromap
CDE Resistivity Map
Canon Stepper
SSI Track
CD Linewidth
Overlay
Branson Asher
Discipline
PVD/Plasma Etch CVD/PECVD Wet Etch/CMP
CVC601
Drytech Quad
Lam490
Lam4600
Nanospec
Tencore P2
ASM 6”LPCVD
P-5000
Nanospec
Spectromap
Varian 350D
While in each discipline the students will
Process lots requiring steps in that discipline
Perform follow up Inspection and Metrology
Investigate and Update SPC data
Monitor non-device process metrics
Rochester Institute of Technology
Perform
a “pass down” at the end of (2 weeks)
Microelectronic
Engineering
Track lots in and out of Mesa
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 17
Al Wet Etch
BOE Etch
RCA Clean
Hot Phos Nitride Etch
BOE
Solvent Strip
CMP and CMP Clean
Nanospec
Surfscan
SEM
1-21-2015
CMOS Factory
FACTORY TEAMS - THURSDAY
Red
Group
1. Shrushti
2.
3.
Orange
Group
1. Mrudula
2.
3.
Yellow
Group
1. Prashant
2. Ronak
3.
Green
Group
1. Suresh
2. Ankur
3.
Blue
Group
1. Harshala
2.
3.
Every two weeks groups shift discipline (to the right). For example the red group does
Diffusion week 1&2, Red does Lithography week 3&4, Red does CVD/Plasma week 5&6, etc.
Lithography
Diffusion
Bruce Furnace
AG-RTP
Blue M Oven
Nanospec
Spectromap
CDE Resistivity Map
Canon Stepper
SSI Track
CD Linewidth
Overlay
Branson Asher
Discipline
PVD/Plasma Etch CVD/PECVD Wet Etch/CMP
CVC601
Drytech Quad
Lam490
Lam4600
Nanospec
Tencore P2
ASM 6”LPCVD
P-5000
Nanospec
Spectromap
Varian 350D
While in each discipline the students will
Process lots requiring steps in that discipline
Perform follow up Inspection and Metrology
Investigate and Update SPC data
Monitor non-device process metrics
Rochester Institute of Technology
Perform
a “pass down” at the end of (2 weeks)
Microelectronic
Engineering
Track lots in and out of Mesa
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 18
Al Wet Etch
BOE Etch
RCA Clean
Hot Phos Nitride Etch
BOE
Solvent Strip
CMP and CMP Clean
Nanospec
Surfscan
SEM
1-21-2015
CMOS Factory
EXAMPLE TEAM REPORT AT END OF ROTATION
Discipline: Lithography
Date: Nov 30- Dec 8, 2014
Group Members: Matt McQuillan, Dave Pawlik
Lot Advancement:
F031013 – CC Photo –Changed Stepper Job to Align using TVPA Marks Only
added 2 µm shift to alignment key locations on pg 4/ in process file
F040119 – Resist Strip
F040614 – Active Photo
F031013 – LDDP Photo
F040920 – Resist Strip-Changed Stepper Job to Align using TVPA Marks Only
F040920 – P-Well Photo-Changed Stepper Job to Align using TVPA Marks Only
F030922- Resist Strip
Other: Short Loop Resist Coat Thickness measurement for Coat.rcp, Xpr=1.0 µm
Branson Asher often gives purge timeout error, select continue
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 19
Rochester Institute of Technology
Microelectronic Engineering
Dr. Lynn Fuller
Red (Diffusion) Orange (Lithography) Yellow (Plasma Etch) Green (Implant/CVD) Blue (wet Etch)
Date: 8-26-14
Lot Status Report
Time: 8:00 am
STEP
Next
Operation
Qty
Comments
X
70
ET26
2
ORANGE
IM01
X
46
ET07
4
YELLOW
SUB-CMOS 150
CV01
X
35
IM01
2
GREEN
JOHN GALT
SUB-CMOS 150
ET06
X
26
OX04
3
BLUE
F130207
JOHN GALT
SUB-CMOS 150
OX04
X
9
ET19
4
RED, TUBE 1
F130620
JOHN GALT
SUB-CMOS 150
CL01
X
1
OX05
3
BLUE
F130626
JOHN GALT
ADV-CMOS 150
OX05
X
1
CV02
3
RED, TUBE 4
Lot No
Product
Process / Version
Current
operation
Q
F111208
JOHN GALT
SUB-CMOS 150
PH03
F120825
JOHN GALT
SUB-CMOS 150
F121126
JOHN GALT
F121208
P
ORANGE – determine correct exposure time for lot numbers using MA150 contact exposure
- prepare wafers for testing aluminum plasma etch
- test completed wafers
CMOS Factory
OPERATOR FLOW CHART FOR FACTORY WORK
START
Access
MESA
Lot Status
Continue
A
LOT SELECTION RULES
Do Photo first
Do Oldest Lot Next
Separate Lots Current Step
Match Skill Level
Use Equipment that is Up
Find Queue Status
Step Number
Current Operation
Next Operation
Quantity
No
No
On Hold?
In Queue?
Yes
Yes
Yes
INITIAL QUALITY CHECK
Count Wafers
Check Picture Log Book
Think
Refer to Previous Process Step
Check MESA Move-Out Comments
Prelininary
Quality
Check
Mesa
History
Who Did
Move-In
Do Move-In
Start Run
Timer
Yes
Pass ?
See Lab Instructor
No
See Lab Instructor
On Hold?
Contact Person
Determine What
To Do Next
No
Do Work
Follow MESA
Instructions Exactly
Check
Equipment
Status
Apply Lot
Selection
Rules
Find
Wafers
FINAL QUALITY CHECK
Count Wafers
Check Picture Log Book
Think
Do Results Make Sense?
Final
Quality
Check
Continue
A
No
See Lab Instructor
Yes
Pass ?
Stop Run Timer
Move Out
Record Data
Clean Up
Return Wafers
Return Masks
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 21
END
CMOS Factory
SPC CHARTS
SPC6SC_FO
Field Oxide Thickness
SPC6SC_GOX
Gate Oxide Thickness
SPC6SC_KOX
Kooi Oxide Thickness
SPC6SC_LTO
LTO/TEOX Oxide Thickness
SPC6SC_MTL
Metal Thickness
SPC6SC_N1
Nitride Thickness (1500Å)
SPC6SC_N2
Nitride Thickness (3500Å)
SPC6SC_PADPad Oxide Thickness
SPC6SC_POL
Poly Thickness
SPC6SC_WO
Well Oxide Thickness
SPC6SCPROS
Poly Sheet Resistance
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 22
CMOS Factory
NWA QUALITY ANALYST, SPC CHART
Pad Oxide
Target 500Å
USL 600Å
LSL 400Å
Mean 535Å
Std Dev 25Å
Cpk 0.8648
Cp 1.332
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 23
CMOS Factory
MANUFACTURING IMPROVEMENT
If no factory lots are available in a specific discipline then group will do
manufacturing improvement projects.
For Example:
BOE – Etch rate verification
RTP – Tool operation and recipe verification
PECVD – Tool operation and deposition rate verification,TEOS Oxide
Resist Coat Thickness Measurement using Spectromap for Coat.rcp and
CoatMtl.rcp Recipes used by Factory
SPC Chart verification, evaluation and process capability improvement
Verify all MESA picture documents are correct
Verify MESA instructions are correct
Rochester Institute of Technology
Microelectronic Engineering
© January 20, 2015, Dr. Lynn Fuller, Professor
Page 24