Exceptions
Exceptions





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Exception Types
Exception Handling
Vectoring
Interrupts
Interrupt Handlers
Interrupt Priorities
Interrupt applications
6-2
Exception Types

Exceptions caused by executing an instruction

Software interrupts
 Undefined instruction
 Prefetch abort (accessing an invalid address)

Exceptions caused as a side effect of an instruction
 Data

abort
Exceptions unrelated to instruction execution
 Reset
 IRQ
- Usually generated by external peripherals
 FIQ - Usually generated by external peripherals
6-3
Exception Handling

When an exception occurs
 The
exception is latched.
 The normal program execution is stopped.
 The current PC and CPU mode is preserved.
 The PC is forced to the corresponding vector location
 Program execution continues from this point
 For the IRQ and FIQ exceptions


when the exception has been processed the environment
restored and the PC reloaded so that the original program
can resume.
The event that caused the exception must be cleared.
6-4
ARM 7 Exception handling
When an exception occurs, the CPU will change modes and the PC
will be forced to an exception vector. The vector table starts from
address zero with the reset vector, and then has an exception vector
every four bytes.


Each operating mode has an associated interrupt vector. When the
processor changes mode the PC will jump to the associated vector.
NB: there is a missing vector at 0x00000014.
6-5
Exception Priorities
If two or more exceptions are asserted they will be served
in the following order
6-6
Exception Vectors
; Taken from the assembler startup file.
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors
;
LDR
LDR
LDR
LDR
LDR
NOP
LDR
LDR
LDR
PC,
PC,
PC,
PC,
PC,
Reset_Addr
Undef_Addr
SWI_Addr
PAbt_Addr
DAbt_Addr
; Reserved Vector
PC, IRQ_Addr
PC, [PC, #-0x0120]
PC, FIQ_Addr
; Vector from VicVectAddr
6-7
Cont.
Reset_Addr
Undef_Addr
SWI_Addr
PAbt_Addr
DAbt_Addr
DCD
DCD
DCD
DCD
DCD
DCD
Reset_Handler
Undef_Handler
SWI_Handler
PAbt_Handler
DAbt_Handler
0
Address
IRQ_Addr
FIQ_Addr
DCD
DCD
IRQ_Handler
FIQ_Handler
Undef_Handler
SWI_Handler
PAbt_Handler
DAbt_Handler
IRQ_Handler
FIQ_Handler
B
B
B
B
B
B
Undef_Handler
SWI_Handler
PAbt_Handler
DAbt_Handler
IRQ_Handler
FIQ_Handler
; Reserved
;Tight loops
6-8
;
Reset Handler
EXPORT
Reset_Handler
Reset_Handler
; Clock Setup --IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
LDR
R0, =SCB_BASE
MOV
R1, #0xAA
MOV
R2, #0x55
;
Configure and Enable PLL
LDR
R3, =SCS_Val
STR
R3, [R0, #SCS_OFS]
IF
OSC_Loop
(SCS_Val:AND:OSCEN) != 0
LDR
R3, [R0, #SCS_OFS]
ANDS
R3, R3, #OSCSTAT
BEQ
OSC_Loop
; Enable main oscillator
; Wait for main oscillator
ENDIF
ETC.
6-9
Interrupts
Two interrupt
request inputs to the
CPU
 FIQ - fast interrupt
request
 FIQ higher priority
than IRQ

Two interrupt
request inputs.
n implies not i.e. active low.
6-10
ARM 7 Interrupts


Two interrupt sources FIQ and IRQ
FIQ has priority over IRQ
 An
IRQ handler can be interrupted by an FIQ but not
the other way round.


Normally only have one interrupt source using
the FIQ input.
To support multiple interrupt sources on IRQ
1.
2.

logically OR together and then in the interrupt
handler poll each device (this is slow!), or
Use a Vectored Interrupt Controller (VIC)
The LPC23XX devices use a VIC
6-11
The VIC

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The VIC provides support for
up to 32 interrupt sources
16 priority levels (fixed
hardware priority within a level)
the 32 inputs can be
designated as either FIQ or as
vectored IRQ interrupts.
A priority can be assigned to
each of the separately
vectored IRQs
FIQ
IRQ
VIC
………..
.
32 interrupt
sources
FIQ has higher
priority than IRQ
6-12
FIQ request

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The VIC ORs all the requests to produce the FIQ
signal to the ARM processor.
Remember the FIQ has one vector location only.
Normal to only assign one input to the FIQ otherwise would need the FIQ handler to poll the
VIC to find the interrupting signal source.
The shortest latency is achieved when only one
request is classified as FIQ
Leaving the FIQ handler
 The
interrupt request must be cleared before
returning from the interrupt handler.
6-13
Vectored IRQ

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
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The VIC ORs all the vectored IRQ requests together to
produce the IRQ signal to the ARM7 processor.
The VIC has a table of interrupt address handlers for
each IRQ interrupt source.
When the IRQ is asserted to the ARM7 the address
corresponding to the interrupt source is copied from the
table into a special VICAddress register which is then
accessed by the IRQ handler to go to the correct
interrupt handler.
Leaving a vectored IRQ


The interrupt request must be cleared before returning from the
interrupt handler AND
a dummy write to the VIC to signal the end of the current IRQ
6-14
IRQ Vector instruction

The instruction placed on the IRQ vector must
load the contents of the Vector address register
into the PC
LDR PC,[PC,#-0xFF0]
6-15
Interrupts diagrammatically
Each interrupt is
individually enabled
Interrupt
signals from
the 32
sources
Select which interrupts are
FIQ and which are
vectored IRQ
6-16
Vectored IRQs
IRQ
status[0:31]
6-17
Vectored IRQ process
Each of the 32 interrupt sources from the various peripherals is allocated a
slot in the table. Eg. Timer 0 is allocated the number 4, external interrupt 0
is allocated to 14.
Vector
IRQ
0
1
4
Priority encoder
Timer 0
Address
Vector
Address
Vec 0
Lvl 9
Interrupt Sourcs
Vec 1
Vec 2
Vec 3
14
Lvl 15
X
Vec 4
….
Vec 31
31
6-18
Keil 'C' Language Extensions

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The C Compiler allows designation of a 'C' function
as an Interrupt Handler by adding __irq after the
function header in both the function declaration and
the function definition.
void IntHandler(void) __irq;
The Interrupt handler cannot accept any input
arguments i.e the argument list must be (void)
Also the return type MUST be void.
An interrupt handler function MUST NEVER be
called directly from the main program code!!
The Interrupt Handler is only invoked by the
hardware interrupt vectoring mechanism.
6-19
To summarise the procedure

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

Configure the peripheral i.e. enable interrupts
within the peripheral
Enable the peripheral bit within the VIC
Select to use either the FIQ or IRQ interrupt
Set the priority of the interrupt 0-15 (0 highest)
Set the Vector address for the interrupt handler
 FIQ
- fixed at address 0x0000001C
 IRQ - set vector address in relevant slot of VIC

Write the interrupt handler, which should
terminate by clearing the request before returning.
6-20
Interrupt usage

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Used for non periodic and/or asynchronous
events.
Avoids polling which is potentially wasteful of CPU
processing time.
Allows the main program to be seen as a
background task and the interrupts as higher
priority tasks or events that must take precedence.
Good for responding to events and data input.
Avoids loss of input data which could happen with
polling
6-21
The Interrupt Handler

Interrupt handler routine
 local
variables are created on each invocation
 use static keyword to preserve local variable value
between invocations e.g. static int value = 0;

Data communication between main program and
ISR is via shared global variables.
 this
introduces mutual exclusion problems
 Cannot access a common resource concurrently from
two execution threads (concurrent access)

Other problems - Re-entrancy of functions
 The
ISR calls a function that was being executed
when this interrupt occurred.
6-22
Interrupt Processing

Solutions to the mutual exclusion problem
 disable
the interrupt during the main program access
of the shared variables.
 use a single atomically accessed variable - not
possible in many cases!
 use semaphores and mutexes - requires an
Operating System that supports these features

Solution to the function re-entrancy problem
 Don't
call any functions from the ISR
 Make sure function is re-entrant - not always possible
6-23
Data Buffering and Interrupts

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Decouples main program from interrupt handler
Moves data processing from the interrupt
handler in to the main program
Use of "Circular Buffers" to provide optimum
buffer usage.
Data Buffer
(size = N)
Interrupt Handler
X0
Input data from
peripheral and
store in buffer.
Move Wrptr
pointer and
increment count
X1
Wrptr
X2
Main program
Rdptr
Read data from
buffer and
processes it.
Move Rdptr and
decrement
count
Count = 3
6-24
Interrupt Techniques
 Interrupt Handler
input X
α if (count < N)
{ //store in buffer
Buffer[Wrptr] = X
Wrptr++
if (Wrptr == N)
{
Wptr = 0
}
count++
}
 Part of main program
if (count > 0)
{ //process all data
while (count > 0)
{
val = Buffer[Rdptr]
Rdptr++
if (Rdptr == N)
{
Rdptr = 0
}
count-β
//process val
}
α What if count == N?
}
β What about mutual exclusion?
What are initial values?
6-25
Solution to the mutual exclusion problem
Rdptr++
if (Rdptr == N)
{
Rdptr = 0
}
disable interrupt
count-enable interrupt
//process val

The disabling of interrupts
would not be required if it
could be guaranteed that
the decrement of the count
was an atomic(indivisible)
operation and could not be
interrupted midway through
the operation
}
}
6-26