William Stallings
Computer Organization
and Architecture
6th Edition
Chapter 9
Computer Arithmetic
Arithmetic & Logic Unit
• Performs arithmetic and logical operations on
data.
• Everything else in the computer is there to
service this unit
• Handles integers
• May handle floating point (real) numbers
• May be separate FPU (maths co-processor)
• May be on chip separate FPU (486DX +)
ALU Inputs and Outputs
• Data are presented to the ALU in registers, and the
results of an operation are stored in registers.
• The ALU may also set flags as the result of an operation.
• The control unit provides signals that control the
operation of the ALU and the movement of the data into
and out of the ALU.
Integer Representation
• Only have 0 & 1 to represent everything
• Positive numbers stored in binary
—e.g. 41=00101001
• No minus sign
• No period
• Negative number representation
—Sign-Magnitude
—Two’s complement
Sign-Magnitude
• Left most bit is sign bit
—0 means positive
—1 means negative
• +18 = 00010010
• -18 = 10010010
• Problems
—Need to consider both sign and magnitude in
arithmetic
—Two representations of zero (+0 and -0)
Two’s Complement
• Two’s complement
— Take the Boolean complement of each bit of the integer. i.e., set
each 1 to 0 and each 0 to 1.
— Treating the result as an unsigned binary integer, add 1.
— Example:
– 3 = 00000011
– Boolean complement gives
– Add 1 to LSB
— +3 = 00000011
— +2 = 00000010
— +1 = 00000001
— +0 = 00000000
— -1 = 11111111
— -2 = 11111110
— -3 = 11111101
11111100
11111101
Benefits
• One representation of zero
• Arithmetic works easily (see later)
• Negating is fairly easy
Geometric Depiction of Twos
Complement Integers
若加上k，則往順時針方
若減去k，則往逆時針方
向移動k個位置
向移動k個位置
Negation Special Case 1
•
•
•
•
•
•
•
0=
00000000
Bitwise not
11111111
Add 1 to LSB
+1
Result
1 00000000
Overflow is ignored, so:
-0=0
Overflow
—When the result is larger than can be held in the
word size being used.
Negation Special Case 2
•
•
•
•
•
•
-128 =
-10000000
bitwise not
01111111
Add 1 to LSB
+1
Result
10000000
So:
-(-128) = -128 X
Range of Numbers
• 8 bit 2s complement
—+127 = 01111111 = 27 -1
— -128 = 10000000 = -27
• 16 bit 2s complement
—+32767 = 011111111 11111111 = 215 - 1
— -32768 = 100000000 00000000 = -215
• N bits 2s complement
—+(2n-1-1)
—-(2n-1)
Conversion Between Lengths
• Positive number pack with leading zeros
—+18 =
00010010
—+18 = 00000000 00010010
• Negative numbers pack with leading ones
—-18 =
10010010
—-18 = 11111111 10010010
• i.e. pack with MSB (sign bit)
—Sign extension
Addition and Subtraction
• Normal binary addition
• Monitor sign bit for overflow
• Take twos compliment of subtrahend and add to
minuend
—i.e. a - b = a + (-b)
• So we only need addition and complement
circuits
Addition of Numbers in Twos Complement
Representation
Subtraction of Numbers in Twos Complement
Representation (M-S)
Subtraction of Numbers in Twos Complement
Representation (M-S)
Overflow
• Overflow
— The result of addition is larger than can be held in the word
size.
• No overflow when adding a positive and a negative
number
• No overflow when signs are the same for subtraction
• Overflow occurs when the value affects the sign:
— overflow when adding two positives yields a negative
— or, adding two negatives gives a positive
— or, subtract a negative from a positive and get a negative
— or, subtract a positive from a negative and get a positive
• Effects of Overflow
— An exception (interrupt) occurs
– Control jumps to predefined address for exception
Hardware for Addition and Subtraction
Multiplication
•
•
•
•
Complex
Work out partial product for each digit
Take care with place value (column)
Add partial products
Multiplication Example
•
1011 Multiplicand (11 dec)
•
x 1101 Multiplier
(13 dec)
•
1011 Partial products
•
0000
Note: if multiplier bit is 1 copy
• 1011
multiplicand (place value)
• 1011
otherwise zero
• 10001111 Product (143 dec)
• Note: need double length result
Unsigned Binary Multiplication
Execution of Example
Flowchart for Unsigned Binary
Multiplication
Multiplying Negative Numbers
• Solution 1
—Convert to positive if required
—Multiply as above
—If signs were different, negate answer
• Solution 2
—Booth’s algorithm
Comparison of Multiplication of Unsigned and
Twos Complement Integer
部分積以2n bit表示
可解決被乘數為負值的
問題，但若乘數為負值
時，仍無解
Booth’s Algorithm
Example of Booth’s Algorithm
Examples Using Booth’s Algorithm
Examples Using Booth’s Algorithm (cont.)
Division
• More complex than multiplication
• Negative numbers are really bad!
• Based on long division
Division of Unsigned Binary Integers
00001101
Divisor
1011 10010011
1011
001110
Partial
1011
Remainders
001111
1011
100
Quotient
Dividend
Remainder
Flowchart for Unsigned Binary Division
Real Numbers
• Numbers with fractions
• Could be done in pure binary
— 1001.1010 = 23 + 20 +2-1 + 2-3 =9.625
• Where is the binary point?
— Fixed-point notation
– Very limited
+ Very large numbers cannot be represented, nor can very small
fractions.
— Floating-point notation
– Scientific notation
E
SB
–
–
–
–
Sign: plus or minus
Significand S
Exponent E
Base B
Sign bit
Floating Point
Biased
Exponent
Significand or Mantissa
• +/- .significand x 2exponent
• Point is actually fixed between sign bit and body of
mantissa
— There is one bit to the left of the radix point.
• Exponent value is biased representation
— A fixed value is subtracted from the field to get the true exponent value
— The bias equals (2k-1-1)
Floating Point Examples
Signs for Floating Point
• Exponent is in excess or biased notation
—e.g. Excess (bias) 127 means
—8 bit exponent field
—Pure value range 0-255
—Subtract 127 to get correct value
—Range -127 to +128
• Significand also called the mantissa
Normalization
• FP numbers are usually normalized
— i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
— Since it is always 1 there is no need to store it
— e.g. 3.123 x 103
— The normalized nonzero number is one in the form
 1.bbb...b  2
E
— See Fig. 9.18b
– The sign is stored in the first bit of the word
– The first bit of the true significand is always 1 and need not be
stored in the significand field.
– The value 127 is added to the true exponent to be stored in the
exponent field.
– The base is 2.
FP Ranges
• For a 32 bit number
— Using 2s complement integer representation
 231 ~ 231  1
— Using 8 bit exponent, 23 bit significand
– Negative number –(2-2-23)*2128~-2-127
– Positive number: 2-127~(2-2-23)*2128
— Five regions on the number line are not included in these
ranges:
–
–
–
–
–
Negative overflow
Negative underflow
Zero
Positive underflow
Positive overflow
• Accuracy
— The effect of changing lsb of mantissa
— 23 bit mantissa 2-23  1.2 x 10-7
— About 6 decimal places
Expressible Numbers
IEEE 754
• Standard for floating point storage
—32 bit single precision
—64 bit double precision
• 8 and 11 bit exponent respectively
• 23 and 52 bit significand respectively
• The exponent is biased,
—the rang of exponents is -126~+127，-1022~+1023
—exponent 與significand均為零時， 由 sign決定為
positive or negative zero.
—Exponent均為1，significand為零時,由 sign決定為正
負無窮大
IEEE 754 Formats
IEEE 754 format parameter
Interpretation of IEEE 754 FP numbers
Example 1
• (a) Convert the decimal number -1.5 to a 32-bit
floating-point number with IEEE 754 format.
(b) Convert a 32-bits IEEE 754 format floatingpoint number 43A0C000 to the decimal number.
• Solution:
• (a) 1.5=1.12=1.1*20
S=1, C=E+127=127=01111111,
F=1000 0000 0000 0000 0000 000
(b)43A0C000=0100 0011 1010 0000 1100 0000
0000 00002
S=0, C=10000111=135=E+127, =>E=8,
F= 0100 0001 1000 0000 0000
1.01000001102*28=101000001.12= 321.5
Example 2
• Convert the decimal number -1.5 to a 32-bit
floating-point number with IBM S/390 format.
• Solution:
—Base of 16, 7 bit exponent, 24 bit significand
—-1.5=-1.8(16)=-0.18*161
—S=1, C=E+64=1+64=65=100 0001
F=0001 1000 0000 0000 0000 0000
—The IBM S/390 format is
1 100 0001 0001 1000 0000 0000 0000 0000
Floating-point Arithmetic
• A FP operation may produce one of these
conditions:
—Exponent overflow
—Exponent underflow
—Significand underflow
—Significand overfolw
FP numbers and arithmetic operations
FP Arithmetic +/•
•
•
•
Check for zeros
Align significands (adjusting exponents)
Add or subtract significands
Normalize result
FP Addition & Subtraction Flowchart
FP Arithmetic x/
•
•
•
•
•
•
Check for zero
Add/subtract exponents
Multiply/divide significands (watch sign)
Normalize
Round
All intermediate results should be in double
length storage
Floating Point Multiplication
Floating Point Division
Precision Considerations
• Guard bit
—Used to pad out the right end of the significand with
0s.
• Rounding
—When the result is put back into the floating-point
format, the extra bits must be disposed of.
—IEEE standard lists four alternative approaches:
– Round to nearest
+ 使用最接近結果的表示值(四捨五入)
– Round toward +∞
– Round toward –∞
– Round toward 0
+ 單純的將多餘的位元截斷。
IEEE standard for binary FP arithmetic
• Infinity
—The limiting case of real arithmetic.
• Quiet and Signaling NaNs
—Signaling NaN afford values for uninitialized variables
and arithmetic-like enhancement.
—Quiet NaN propagates through almost every
arithmetic operation without signaling an exception.
• Denormalized Numbers
—To handle cases of exponent underflow.