Chapter 4
Channel Coding and Error
Control
1
Outline









Introduction
Block Codes
Cyclic Codes
CRC (Cyclic Redundancy Check)
Convolutional Codes
Interleaving
Information Capacity Theorem
Turbo Codes
ARQ (Automatic Repeat Request)



Stop-and-wait ARQ
Go-back-N ARQ
Selective-repeat ARQ
2
Introduction
Antenna
Information to
be transmitted
Source
coding
Channel
coding
Modulation
Transmitter
Air
Antenna
Information
received
Source
decoding
Channel
decoding
Demodulation
Receiver
3
Forward Error Correction (FEC)


The key idea of FEC is to transmit enough
redundant data to allow receiver to recover
from errors all by itself. No sender
retransmission required
The major categories of FEC codes are





Block codes
Cyclic codes
Reed-Solomon codes (Not covered here)
Convolutional codes, and
Turbo codes, etc.
4
Linear Block Codes






Information is divided into blocks of length k
r parity bits or check bits are added to each block (total
length n = k + r)
Code rate R = k/n
An (n, k) block code is said to be linear if the vector sum
of two codewords is a codeword
Tradeoffs between
 Efficiency
 Reliability
 Encoding/Decoding complexity
All arithmetic is performed using Modulo 2 Addition
0 0 1
1
0
0
1
1
0
1
1
0
5
Linear Block Codes

The uncoded k data bits be represented by the m
vector:
m=(m1, m2, …, mk)
The corresponding codeword be represented by the nbit c vector:
c=(c1, c2, …ck, ck+1, …, cn-1, cn)

Each parity bit consists of weighted modulo 2 sum of
the data bits represented by  symbol for Exclusive
OR or modulo 2-addition
6
Linear Block Codes
K- data and r = n-k redundant bits
c1  m1

c2  m2
...

ck  mk
c  m p
k 1
1 1( k 1)  m2 p2 ( k 1)  ...  mk pk ( k 1)

...

cn  m1 p1n  m2 p2 n  ... mk pkn
7
Linear Block Codes: Example
Example: Find linear block code encoder G if code generator
polynomial g(x)=1+x+x3 for a (7, 4) code; n = total number
of bits = 7, k = number of information bits = 4, r = number
of parity bits = n - k = 3
 x3 
p1  Re 
 1  x  110
3
1  x  x 
 x4 
2
p2  Re 

x

x
 011
3
1  x  x 


x5
2
p3  Re 

1

x

x
 111
3
1  x  x 
 x6

2
p4  Re 

1

x
 101
3
1  x  x 
1000| 110
0100| 011
  [ I | P]
G
0010| 111


0001
|
101


I is the identity matrix
P is the parity matrix
8
Linear Block Codes: Example

The Generator Polynomial can be used to determine the
Generator Matrix G that allows determination of parity
bits for a given data bits of m by multiplying as follows:
1000110
0100011
  [1011| 100]
c  m.G  [1011] 
0010111


0001101


Data

Data Parity
Other combinations of m can be used to determine all other
possible code words
9
Linear Block Codes
 Linear Block Code
The block length C of the Linear Block Code is
C=mG
where m is the information codeword block length, G is the
generator matrix.
G = [Ik | P]k × n
where Pi = Remainder of [xn-k+i-1/g(x)] for i=1, 2, .., k, and I
is unit or identity matrix.
 At the receiving end, parity check matrix can be given as:
H = [PT | In-k ], where PT is the transpose of the matrix P.
10
Linear Block Codes
Example: Find linear block code encoder G if
code generator polynomial g(x) with k data
bits, and r parity bits = n - k
1 0 0 P1 


0 1 0 P2 
G  I | P   

 


k
0 01P 

where
n k i 1


x
i
P  Remainder of 
, for i  1, 2, , k

 g ( x) 
11
Block Codes: Linear Block Codes
Message
vector m
Generator
matrix G
Transmitter
Code
Vector C
Air
Code
Vector C
Parity
check
matrix HT
Null
vector 0
Receiver
Operations of the generator matrix and the parity check matrix

Consider a (7, 4) linear block code, given by G as
1000| 110
0100| 011

G
0010| 111


0001
|
101


1011| 100
P  
T

H 

1110
|
010
 
I
 n k  0111| 001


For convenience, the code vector is expressed as
c  m | c p 
T
Where c p  mP is an (n-k)-bit parity check vector
12
Block Codes: Linear Block Codes
Define matrix
HT
P 
as H   
 I n k 
T
Received code vector x = c  e, here e is an error
vector, the matrix HT has the property
P 
cH  m | c p 

I
 n k 
 m P cp  cp  cp  0
T


13
Block Codes: Linear Block Codes
 The transpose of matrix HT is H  PT I nk 
 Where In-k is a n-k by n-k unit matrix and PT is the
transpose of parity matrix P.
 H is called parity check matrix.
 Compute syndrome as s = x HT =( c  e ) * HT
= cHT  eHT = eHT
14
Linear Block Codes
 If S is 0 then message is correct else there are errors in it,
from common known error patterns the correct message
can be decoded.

For the (7, 4) linear block code, given by G as
1000| 111
0100| 110

G
0010| 101


0001| 011

1110| 100


H  1101| 010
1011| 001
For m = [1 0 1 1] and c = mG = [1 0 1 1| 0 0 1]. If there is
no error, the received vector x = c, and s = cHT = [0, 0, 0]
15
Linear Block Codes

Let c suffer an error such that the received vector
x =c  e =[ 1 0 1 1 0 0 1 ]  [ 0 0 1 0 0 0 0 ]
=[ 1 0 0 1 0 0 1 ]
111
Then, Syndrome
s = xHT


110


101


011
  [101]  ( eH T )
 1001| 001 
  


100


010


001
 This indicates error position, giving the corrected
vector as [1011001]
16
Cyclic Codes
It is a block code which uses a shift register to perform
encoding and decoding the codeword with n bits is expressed
as:
c(x)=c1xn-1 +c2xn-2……+ cn
where each coefficient ci (i = 1, 2,.., n) is either a 1 or 0
The codeword can be expressed by the data polynomial m(x)
and the check polynomial cp(x) as
c(x) = m(x) xn-k + cp(x)
where cp(x) = remainder from dividing m(x) xn-k by
generator g(x)
17
Cyclic Codes




Let m(x) be the data block and g(x) be the polynomial
divisor, we have xn-k m(x)/g(x) = q(x) + cp(x) /g(x)
The transmitted block is c(x) = xn-k m(x) + cp(x) 
c(x) / g(x) = q(x)
If there are no errors the division of c(x) by g(x) produces
no remainder.
If one or more bit errors, then the received block c’(x) will
be of the form c’(x) = c(x) + e(x) and the error pattern is
detected from known error syndromes s(x) = e(x)/g(x)
The syndrome value s(x) only depends on the error bits
 To be able to correct all single and double bits errors
the relationship is (n + n(n-1)/2) ≤ (2n-k – 1)
18
Cyclic Code: Example

Example : Find the codeword c(x) if m(x) = 1 + x + x2 and
g(x) = 1 + x + x3, for (7, 4) cyclic code

We have n = total number of bits = 7, k = number of
information bits = 4, r = number of parity bits = n - k = 3
 m( x ) x n  k 
c p ( x)  rem 

g
(
x
)


5
4
3
x  x  x 
 rem  3
x

 x  x 1 

Then,
c( x)  m( x) xnk  c p ( x)  x  x 3  x4  x5
= 0111010
19
Cyclic Code: Example


Example : Let m(x) = 1 + x + x2 and g(x) = 1 + x + x3, for (7,
4) cyclic code
Assume e(x) = 1000000. The received block c’(x) = 1111010

We have s(x) = e(x)/g(x) = x2 + 1. Therefore, s = 101.
According to Table 1(b), we have the error pattern
1000000

Now, supposed the received block is 0111011, or
c’(x) = x5 +x4 + x3 + x + 1. Find s(x) and the error pattern.
20
Table 1: A Single-Error-Correcting (7,4)
Cyclic Code
(a) Table of valid codewords
Data Block
Codeword
0000
0000000
0001
0001011
0010
(b) Table of syndromes for single-bit errors
Error pattern E
Syndrome S
0000001
001
0010110
0000010
010
0011
0011101
0000100
100
0100
0100111
0001000
011
0101
0101100
0010000
110
0110
0110001
0111
0111010
0100000
111
1000
1000101
1000000
101
1001
1001110
1010
1010011
1011
1011000
1100
1100010
1101
1101001
1110
1110100
1111
1111111
Cyclic Redundancy Check (CRC)

Cyclic redundancy Code (CRC) is an error-checking code

The transmitter appends an extra n-k-bit sequence to
every frame called Frame Check Sequence (FCS). The
FCS holds redundant information about the frame that
helps the receivers detect errors in the frame

Transmitter: For a k-bit block, transmitter generates an
(n-k)-bit frame check sequence (FCS). Resulting frame of
n bits is exactly divisible by predetermined number

Receiver: Divides incoming frame by predetermined
number. If no remainder, assumes no error
22
Cyclic Redundancy Check (CRC)

Generator polynomial is divided into the message
polynomial, giving quotient and remainder, the
coefficients of the remainder form the bits of final CRC

Define:
Q – The original frame (k bits) to be transmitted
F – The resulting frame check sequence (FCS) of n-k bits
to be added to Q (usually n = 8, 16, 32)
J – The cascading of Q and F
P – The predefined CRC generating polynomial
The main idea in CRC algorithm is that the FCS is
generated so that J should be exactly divisible by P
23
Cyclic Redundancy Check (CRC)

The CRC creation process is defined as follows:

Get the block of raw message

Left shift the raw message by n-k bits and then divide it
by P

Get the remainder R as FCS

Append the R to the raw message. The result J is the
frame to be transmitted J = Q xn-k + F (= R)



J should be exactly divisible by P
Dividing Q  xn-k by P gives Q  xn-k/P = Q + R/P

Where R is the reminder

J = Q  xn-k + R. This value of J should yield a zero
reminder for J/P
24
Common CRC Codes
Code-Parity
check bits
Generator polynomial g(x)
CRC-12
x12 +x11+x3+x2+x+1
CRC-16
x16 +x15+x2+1
CRC-CCITT
x16 +x12+x5+1
CRC-32
x32 +x26+x23+x22+x16
+x12+x11+x10+x8+x7+x5+x4+x2+x+1
25
CRC Using Polynomials

All of the following errors are not divisible by a
suitably chosen g(x)






All single-bit errors, if g(x) has more than one nonzero
term
All double-bit errors, if g(x) has a factor with three
terms
Any odd number of errors, as long as g(x) contains a
factor (x +1)
Any burst errors with length is less than or equal to n
–k
A fraction of error bursts of length n – k + 1; the
fraction equals 1 – 2-(n-k-1)
A fraction of error bursts of length greater than n – k
+ 1; the fraction equals 1 – 2-(n-k)
26
Convolutional Codes






Most widely used channel code
Encoding of information stream rather than information
blocks
Decoding is mostly performed by the Viterbi Algorithm
(not covered here)
The output constraint length K for a convolution code is
defined as K = M + 1 where M is the maximum number
of stages in any shift register
The code rate r is defined as r = k/n where k is the
number of parallel information bits and n is the the
number of parallel output encoded bits at one time
interval
A convolution code encoder with n=2 and k=1 or code
rate r = 1/2 is shown next
27
Convolutional Codes: (n = 2, k = 1,
M = 2) Encoder
1
1
yy11
1
0
Input
x
0
D1
D101
Output
c
D2
D02
1
y1y22
0
y1 = x  D1 D2
y2 = x  D2
D1, D2 - Registers
Input x:
1
Output y1, y2: 11
1
01
1
10
0
01
0
11
0
00
…
…
Input x:
1
Output y1, y2: 11
0
10
1
00
0
10
0
11
0
00
…
…
28
State Diagram
10/1
11
01/0
01/1
10/0
10
01
00/1
11/1
00
11/0
00/0
29
Tree Diagram
00
0
……
First input
00
00
11
…11001
11
11
10
01
10
10
00
1
First
output
… 10 11 11 01 11
11
00
01
01
10
11
11
01
00
01
00
11
10
01
11
01
10
10
00
01
10
30
Trellis
… 11 0 0 1
00
10 11 11 01 11
00
00
00
00
11
11
10
00
10
11
10
11
01
01
01
11
11
11
10
11
10
01
11
11
11
01
10
11
11
…
00
10
01
01
00
10
00
10
01
01
00
00
10
00
10
10
01
00
00
01
01
01
10
11
31
Interleaving
a1, a2, a3, a4, a5, a6, a7, a8, a9, …
Read
Input Data
Interleaving
a1,
a5,
a9,
a13,
a2, a3,
a4
a6,
a7, a8
a10, a11, a12
a14, a15, a16
Write
a1, a5, a9, a13, a2, a6, a10, a14, a3, …
Transmitting Data
Through Air
a1, a5, a9, a13, a2, a6, a10, a14, a3, …
De-Interleaving
Output Data
Write
Received Data
a1,
a5,
a9,
a13,
a2, a3,
a4
a6,
a7, a8
a10, a11, a12
a14, a15, a16
Read
a1, a2, a3, a4, a5, a6, a7, a8, a9, …
32
Interleaving (Example)
Burst
error
De-Interleaving
Output Data
0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0,…
Read
Write
Transmitting
Data
0,
0,
0,
1,
1,
1,
1,
0,
0,
0,
0,
0,
0
0
0
0
0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, …
Discrete errors
33
Automatic Repeat Request (ARQ)
Source
Encoder
Transmitter
Transmit
Controller Modulation
Receiver
Channel
Demodulation
Destination
Decoder
Transmit
Controller
Acknowledge
34
Stop-And-Wait ARQ (SAW ARQ)
Retransmission
Transmitting
Data
1
2
Received
Data
1
Output Data
1
3
3
2
Time
3
Time
Error
2
3
Time
ACK: Acknowledge
NAK: Negative ACK
35
Go-Back-N ARQ (GBN ARQ)
Go-back 3
Transmitting
Data
Received Data
1 2 3 4 5 3 4 5 6 7 5
1 2
3 4
Error
Output Data
Go-back 5
1 2
Time
5
Time
Error
3 4
5
Time
 Sender needs to buffer all the packets have not been acknowledged.
 Only a buffer of one packet size is needed at the receiver.
36
Selective-Repeat ARQ (SR ARQ)
Retransmission Retransmission
Transmitting
Data
Received Data
1 2 3 4 5 3 6 7 8 9 7
1 2
4 5 3 6
Error
Buffer
1 2
Output Data
1 2
Time
8 9 7
Error
4 5 3 6
8 9 7
3 4 5 6
7 8 9
Time
Time
Time
 Receiver needs a large memory to buffer and reorder packets
before passing to the upper layer.
37
Homework

Problems: 4.4, 4.7, 4.10, 4.12

Practice in home: 4.1, 4.6, 4.17,4.19, 4.24
38