EE323000 積體電路設計導論
Introduction to HSPICE
Tutor ： Chien-Chen Lin
2015/4/7
What is SPICE

Simulation Program with Integrated Circuit Emphasis
SPICE
SPICE2 SPICE2G.6 SPICE3 etc
P-Spice
H-Spice
Star-HSpice
SPECTRE
SBT-Spice

PSPICE 、SPECTRE use graphical interface like

HSPICE use text interface like
Mn vd vg vss vss n_18 w=1u l=0.18u m=1
device name net1 net2……. type parameter value
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 2
Prepare files
Hspice
Library
cic018.l
LARC_Memory (Prof. M. F. Chang)
Netlist
inv.spi
EE Dept., NTHU, Taiwan
Simulation file
Hw1.sp
HSPICE # 3
Example (inverter analysis)
* title
VDD
.prot
.lib “cic018.l” TT
Set up
Z
.unprot
A
.inc “inv.spi”
.option post
x1 VIN VOUT VDD GND inv
VSS
Circuit description
3.3V
C1 out 0 0.05p
v1 VDD 0 1.8
v2 GND 0 0
Power supply
X1
v3 VIN 0 0
.dc v3 0 1.8 0.01
Analysis
.probe V(VOUT)
.end
LARC_Memory (Prof. M. F. Chang)
File end
EE Dept., NTHU, Taiwan
HSPICE # 4
Basic syntax

第一行 HSPICE 不會讀到，一般用來註明TITLE 。

用 ﹡來當作整行註解；用＄來當作該行部分註解。

SPICE code不分大小寫，且擺放位置先後順序可對調。

Net用0 、gnd來命名皆表示該 net 接地。

結尾要打.END 。
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 5
Device table

Device table
LARC_Memory (Prof. M. F. Chang)
Unit table
EE Dept., NTHU, Taiwan
HSPICE # 6
Device

Resistor
Rxxx net1 net2 R=? Ω
Ex ： R1 v1 v2 100

Inductor
Lxxx net1 net2 L=? H
Ex ： L2 v3 v4 1n

Capacitor
Cxxx net1 net2 C=? F
Ex ： C3 v5 v6 2p
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 7
Device

Mxxx drain gate source body channel-type width length m
． NMOS body is the most negative bias (GND)
． PMOS body is the most positive bias (VDD)

Ex ： Inverter
MP Z A VDD VDD p_18 w=1u l=0.18u m=2
MN Z A GND GND n_18 w=1u l=0.18u m=1
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 8
Corner

FF: Fast NMOS and Fast PMOS

TT: Typical NMOS and PMOS

SS: Slow NMOS and Slow PMOS

SF: Slow NMOS and PMOS

FS: Fast NMOS and Slow PMOS
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 9
Sub-circuit

.subckt sub-circuit name port name
Your sub-circuit schematic
.ends

Ex ： Inverter (inv.spi)
*title
.subckt inv A Z VDD GND
MP Z A VDD VDD pch w=1u l=0.35u m=2
MN Z A GND GND nch w=1u l=0.35u m=1
.ends
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 10
Example (inverter DC analysis)
* title
VDD
.prot
.lib “cic018.l” TT
Set up
Z
.unprot
A
.inc “inv.spi”
.option post
VSS
x1 VIN VOUT VDD GND inv Circuit description
1.8V
C1 out 0 0.05p
v1 VDD 0 1.8
v2 GND 0 0
Power supply
X1
v3 VIN 0 0
.dc v3 0 1.8 0.01
Analysis
.probe V(VOUT)
.end
LARC_Memory (Prof. M. F. Chang)
File end
EE Dept., NTHU, Taiwan
HSPICE # 11
Example (inverter DC analysis)
* title
VDD
.prot
.lib “cic018.l” TT
Set up
Z
.unprot
A
.inc “inv.spi”
.option post
VSS
.param vin = 0
Circuit description
1.8V
x1 VIN VOUT VDD GND inv
C1 out 0 0.05p
v1 VDD 0 1.8
Power supply
X1
v2 GND 0 0
v3 VIN 0 ‘vin’
Analysis
.dc vin 0 1.8 0.01
.probe V(VOUT)
.end
LARC_Memory (Prof. M. F. Chang)
File end
EE Dept., NTHU, Taiwan
HSPICE # 12
Source

Voltage source
Vxxx net1 net2 DC=? V AC=? V
Ex ： Vsupp vdd vss DC=3.3
Ex ： Vin vi vss DC=2 AC=1
Vxxx net1 net2 SIN vdc vamp freq td df phase
Ex： VSIN in 0 SIN 1.65 0.1 1Meg
Vxxx net1 net2 PULSE v1 v2 td tr tf pw period
Ex： VPULSE in 0 PULSE 0 3.3 1n 0.1n 0.1n 0.9n 2n
Vxxx net1 net2 PWL t1 v1 t2 v2 t3 v3……..
Ex： VPWL in 0 PWL 0 0 1n 0 1.1n 3.3 2n 3.3 2.1n 0 3n 0

Current source
Ixxx net1 net2 DC=? A AC=? A
LARC_Memory (Prof. M. F. Chang)
Ex ： Isupp vdd vss DC=3.3
EE Dept., NTHU, Taiwan
HSPICE # 13
PULSE & PWL
V0 vp 0 (1.8 0 0.5n 0.1n 0.1n 0.9n 2n)
v1
td
pw
period
v2
tf
tr
V0 vpwl 0 PWL( 0n 1.8 1n 0 2n 0 2.1n 1.8)
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 14
Analysis

.OP: Analyze operation point of nodes in circuit. -> *.lis
Syntax.
Example.

.DC: DC analysis to sweep parameter, source and temperature
values.
Syntax.
Example.

- > *.sw*
.DC
.DC
<var1> <start> <stop> <step>
Vgs
0
5
0.1
.AC: AC analysis to sweep frequency.
Syntax.
Example.

.OP
.OP
.AC
.AC
<DEC/LIN>
DEC
<np>
10
.Tran: Transient analysis to sweep time.
Syntax.
Example.
.Tran
.Tran
LARC_Memory (Prof. M. F. Chang)
<step>
1ns
-> *.ac*
<start> <stop>
1KHz
10MHz
-> *.tr*
<stop>
1us
EE Dept., NTHU, Taiwan
HSPICE # 15
Analysis

.Probe ： Probe the observation will not show in the
result file but can be seen at awaves
.probe V(net) I(device)

.Print ： Print the observation in the result file
.print V(net) I(device)

.Plot ： Plot the observation in the result file (Funny
Plot)
.plot V(net) I(device)
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 16
Optional Analysis

SWEEP: Additional nested sweep analysis. Sweep parameter,
source or temperature values but not model parameters.
Syntax.
<Analysis> SWEEP <var> <start> <stop> <step>
or
<Analysis> SWEEP <var> <DEC/LIN> <np> <start>
<stop>
Example.
.DC Vds 0 5 0.1 SWEEP Vgs 2 5 1
.AC DEC 10 1K 10M SWEEP RL 10K 30K 10K
.Tran 1ns 1us SWEEP TEMP 0 100 10

.ALTER: Alter condition and repeat analysis.
Syntax.
Example.
.ALTER
(usually combines with .param)
.ALTER
.lib ‘cic018.l’ ff
.ALTER
.lib ‘cic018.l’ ss
.END
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 17
Measure

Function from to
Syntax.
.meas <Analysis> <Result_Var> FUNC <V(net)> From To
Ex:
.meas Tran MaxValue MAX V(out) from=1n to=10n
Syntax.
.meas <Analysis> <Result_Var> FUNC <V(net)> AT
Ex:
.meas DC DC_Gain DERIV V(out) at=‘0.5*3.3’

FUNC can be MIN, MAX, AVG, RMS, DERIV, INTEG

PARAM
Syntax. .meas <Analysis> <Result_Var> PARAM=(‘’)
Ex:
.meas AC AC_GAIN PARAM=(‘Vdb(out)-Vdb(in)’)
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 18
Examples

找出output在1n到10n的最高值


.meas Tran MaxValue MAX V(out) from=1n to=10n
找出output在0.5VDD的斜率

.meas DC DC_Gain DERIV V(out) at=‘0.5*3.3’
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 19
Measure

Trigger and Target
Syntax. .meas <Analysis> <Result_Var> TRIG <V(netx)> <val=X>
<Slew> TARG <V(nety)> <val=Y> <Slew>
Ex: .meas tran SettleTime Trig V(out) val=0V rise=1 Targ V(out)
+ val=1V cross=last

Analysis can be DC, AC, Tran

Val means value of V(net)

Slew can be rise, fall, cross (special word “last”)
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 20
Example
.meas tran SettleTime Trig V(out) val=0V rise=1 Targ V(out)
+ val=1V cross=last
Targ val=1V cross=last
Trig val=0v rise=1
LARC_Memory (Prof. M. F. Chang)
Targ val=1V cross=1
EE Dept., NTHU, Taiwan
HSPICE # 21
Measure

Find When
Syntax.
.meas <Analysis> <Result_Var> FIND <V(net)> WHEN
+ <V(net)> Slew
Ex: .meas AC Phase FIND VP(out) WHEN VdB(out)=0 fall=1

Find At
Syntax.
.meas <Analysis> <Result_Var> FIND <V(net)> AT
Ex:
.meas TRAN Volt Find V(out) at=10n
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 22
How to run HSPICE

Make sure all files are in the same folder
you can type ls to check

Enter that folder, type hspice xxx.sp >! xxx.lis
or hspice -i xxx.sp -o xxx.lis

If there is no error, terminal will print out job concluded
otherwise, terminal will print out job aborted
Open xxx.lis file check error. It will tell you everything.
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 23
SPICE explorer

Type sx & at terminal
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 24
SPICE explorer
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 25
SPICE explorer
Double click
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 26
SPICE explorer
Double click
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 27
Basic syntax
* title
(inverter DC analysis)
title
.prot
.lib “mm0355v.l” TT
include library and set corner condition
.unprot
.inc “inv.spi”
.option post
include netlist
waveform post
x1 IN OUT VDD GND inv
call inv sub-circuit
C1 out 0 0.05p
v1 VDD 0 3
voltage source
v2 GND 0 0
v3 IN 0 0
.probe V(OUT)
simulation analysis
output node voltage
.end
file end
.dc v3 0 3 0.01
LARC_Memory (Prof. M. F. Chang)
EE Dept., NTHU, Taiwan
HSPICE # 28