Digital Signal Processing
Basics and AO Back-Ends
Luis A. Quintero
Digital Section Head
Electronics Department
Arecibo Observatory
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Introduction to Digital Signal Processing
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Continuous Signal Acquisition - Transducers
System - World
ELECTRICAL VARIABLE
Resistance, Capacitance,
Voltage, etc
Signal
Conditioning
Transducer
Quantity
Voltage
time
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
time
Sampling
Continuous-time Signal (real signal)
Amplitude
time
Discrete-time Signal
Amplitude
time
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Signal Storage in Computers
1V
time
-1V
- 0.45
+ 0.70
- 0.47
- 0.82
+ 0.30
+ 0.40
- 0.90
…
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
http://www.iusb.edu/
Analog to Digital Converter – Quantization
7
6
5
4
3
2
1
0
time
- 0.45
2
+ 0.70
5
- 0.47
2
- 0.82
1
+ 0.30
A/D
…
4
+ 0.40
4
- 0.90
6
…
…
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Analog to Digital Converter – Quantization
time
2
5
2
…
1
D/A
4
Digital-to-Analog
Converter
4
6
…
http://www.iusb.edu/
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Digital Signal Processing System
Computer
A/D
…
…
Analog-to-Digital
Converter
D/A
Digital-to-Analog
Converter
Data Storage
Data Processing
- Math Operations
- Filters
- Fourier Transform
- Data Format
Computer (Digital System)
- Micro Processor
- DSP (MAC)
- Logic Circuit
- ASIC
- PAL/CPLD
- FPGA
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Sampling Rate – Analog to Digital
Fs = 9 samples/second = 9Hz
time
1 Second
Fs = 19 samples/second = 19Hz
time
Better signal reconstruction
More computer memory / BW and $$
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Analog to Digital Converter - Clock Input
ANALOG
DIGITAL
A/D
…
clk
Stable – jitter
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Clock for digital circuit
Resolution
Resolution: 3bits, 23 = 8 combinations
7
Values from 0
to 7
time
0
Resolution: 4bits, 24 = 16 combinations
15
Values from 0
to 15
time
0
Better signal quantization
More computer memory and $$
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Saturation
• Resolution: 3bits, 23 = 8 combinations
• Too much power to the ADC
• Saturation caused by interference (RFI)
7
time
0
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Sampling – FT, Nyquist and Aliasing
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Sampling – FT, Nyquist and Aliasing
Fs = 200Hz, Ts = 5ms, Fs/2 = 100Hz
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Signal Processing – Adder
4bit adder
4
5
=
4
1bit adder
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Signal Processing – Multiplier
4
8
4
• Multiplication by a Constant – Gain
• Multiplication by -1, Sign change
• Multiplication by a function – e.g. sin/cos - up/down conv.
Things to consider
• Bit growing
• Precision – Approximation Errors
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Signal Processing – Functions, e.g. sin/cos
x[n]
x[n] * sin[n]
sin[n]
…
DATA
n
ADDR
DDS
Phase Increment
Mem - LUT
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Signal Processing – Synchronization
clk
latency
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Filtering – e.g. Finite Impulse Response (FIR)
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Auto Correlation
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Discrete Fourier Transform - DFT
X[k] =FNx[n]
FFT – Fast Fourier Transform, optimized DFT (butterflies)
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Examples with Signals
• Fourier Transform
• Saturation
• Averaging
• Clock Jitter
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, one tone
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, two tones
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, noise effect
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, averaging
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, longer transf.
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, Saturation
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Fourier Transform, Clock Jitter
0% Jitter
40% Jitter
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Applications in Radio Astronomy
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Gregorian Dome Receivers
Ganesan, R. “Telescope Electronics”, May 2006
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Radio Frequency Signal Path
FR O N T
EN D
B AC K -E ND
FI /LO
C O M PU TER
SG
I NAL
N
I
D E TEC TO R
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
D G
I IT IZ ER
Signal Transport – Intermediate Freq.
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Final Stage – Data Acquisition
FR O N T
EN D
B AC K -E ND
FI /LO
C O M PU TER
SG
I NAL
N
I
D E TEC TO R
D G
I IT IZ ER
Data Sampling and Storage
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Bandpass Signals in IF
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Sampling - Nyquist Zones & Analog BW
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Wideband Arecibo Pulsar Processor (WAPP)
• 4 WAPPs
• 1 WAPP = 2 IF Channels
2 Correlators
1 Multiplexer
• 50/100 MHz BW
• auto / crosscorrelations
• Step attenuators
• Technical issues:
Difficult to troubleshoot
Obsolete parts
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Wideband Arecibo Pulsar Processor (WAPP)
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
WAPP Correlators (~1995)
High Performance CMOS Correlator Chip (ASIC)
• 16 Chips per
board
• Autocorrelation /
Crosscorrelation
• 1024 Lags / chip
• 100MSPS each
• “Low Power”
• TTL compatible
http://www.naic.edu/~astro/general_info/correlator/cmos.html
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Complex Sampling
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Arecibo L-band Feed Array
• 7 Receivers
• Dual Polarization
• 14 analog signals
• 1225 – 1525MHz
300MHz BW
• Designed by
Germán Cortés
Medellín (Cornell)
Ganesan, R. “Telescope Electronics”,
May 2006
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Complex Sampling Example: ALFA
1225
1525
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Mock Spectrometer / PDEV (~2007)
Digitizers
Digital Board
Designed and developed by
Jeff Mock
• 8 x AD9430, 12bits ADCs
• 2 x Xilinx Virtex II Pro FPGA
• 2 QDR Mem, 2M x 36
• 1x PowerPC Processor
• Flash & SRAM mems
• 2 x GbE, 2 x RS232
• 5 x SMA (clk, PPS, etc)
• LCD 128x64 pixels
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
PDEV – Architecture
QDR
2Mx36
ADC
ADC
ADC
ADC
GX
Flash /
SRAM
PCIe x8
MGT
2VP70
2 x GbE
PPC
440GX
2 x RS232
ADC
ADC
ADC
ADC
GX
2VP70
QDR
2Mx36
PCIe x8
MGT
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
4 x SMA
PDEV – Mock Spectrometer
CW, Noise,
CW + Noise
TEST
SIGNAL
12
ADC0
CONFIGURATION REGISTERS
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
PROC. INT.
PACKETIZE
ACCUMULATOR
ADC0
STOKES
12
PFB/FFT 16-8k
ADC0
SWITCH
12
GAIN/OFFSET
ADC0
DDC (DDS, LPF)
12
EALFA / PALFA Backend
14 PDEVs*
7 for 7 ALFA pixels (primary)
7 for 7 ALFA pixels (commensal)
14 File servers (4TB)
We own in total 24 PDEVs
DDC (DDS, Mixer, DLPF)
PFB (up to 8192 channels)
Stokes parameters
Accumulation, Packing
* http://www.naic.edu/~phil/talks/vc09/tel_Perf_datatking_09.ppt
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
GALFA Spectrometer / GALSPECT (~2004)
• Backend for the
Arecibo L-band Feed Array
(ALFA) multibeam receiver
• 7 beams, dual polarization
• Outputs*:
Narrowband: 8192channels,
7MHz BW
Wideband: 512 channels,
100MHz BW
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
PR Ultimate Pulsar Processing Instrument ( PUPPI)
• 100/200/400/800MHz BW
• Polyphase Filter Bank
• Dual Pol. 8 bit ADC
• Full Stokes
• 200MB per second
recording (10GbE)
• 0-15.5dB Level Control
• PSRFITS data format
• 1xBee2 + 2xiBOB
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Recording Systems – Mark IV / 5A / 5C / RDBE
• Mark IV + Mark
5A: 1Gbps (125MB
every second)
• RDBE + Mark5C:
4Gbps (500MB
every second)
•eVLBI, AO-UPRCentenial link:
155Mbps all time
512Mbps 24h-6h
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Roach Radar Backend – RRB
• Complex Baseband Digital Down Converter (DDC)
• 50MHz bandwidth max.
• 2 x IF channels (polA/polB)
• Bit selection, 8/4bits
• 1.6Gbps max. data rate
• Doppler correction
• Programmable digital filter
• Hardware (three systems):
ROACH – Signal Proc.
katADC – 2x1.5Gsps@8bit
RAID Server, dual 10GbE
• Fixed parameters: Summer 2012
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Analog v.s. Digital
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Down Conversion
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Digital Down Conversion
SDSS7 - DSP and Backends
Intro, 12 Jul 2013
Questions?
SDSS7 - DSP and Backends
Intro, 12 Jul 2013