Chapter One
Introduction to Pipelined
Processors
Principle of Designing Pipeline
Processors
(Design Problems of Pipeline
Processors)
Job Sequencing and Collision
Prevention
State Diagram
• Suppose a pipeline is initially empty and make
an initiation at t = 0.
• Now we need to check whether an initiation
possible at t = i for i > 0.
• bi is used to note possibility of initiation
• bi = 1  initiation not possible
• bi = 0  initiation possible
State Diagram
bi
1
0
1
0
0
1
State Diagram
• The above binary representation (binary vector)
is called collision vector(CV)
• The collision vector obtained after making first
initiation is called initial collision vector(ICV)
ICVA = (101001)
• The graphical representation of states (CVs) that
a pipeline can reach and the relation is given by
state diagram
State Diagram
• States (CVs) are denoted by nodes
• The node representing CVt-1 is connected to
CVt by a directed graph from CVt-1 to CVt and
similarly for CVt* with a * on arc
Procedure to draw state diagram
1. Start with ICV
2. For each unprocessed state, say CVt-1, do as
follows:
a) Find CVt from CVt-1 by the following steps
1. Left shift CVt-1 by 1 bit
2. Drop the leftmost bit
3. Append the bit 0 at the right-hand end
Procedure to draw state diagram
b) If the 0th bit of CVt is 0, then obtain CV* by
logically ORing CVt with ICV.
c) Make a new node for CVt and join with CVt-1
with an arc if the state CVt does not already
exist.
d) If CV* exists, repeat step (c), but mark the arc
with a *.
State Diagram
101001
State Diagram
Left Shift
101001
010010
State Diagram
Zero  CV*
exists
101001
010010
State Diagram
101001
*
010010
111011
ICV – 101001
CVi – 010010
CV* 111011
OR
State Diagram
101001
*
Left Shift
010010
111011
No CV*
Left Shift
No CV*
100100
110110
State Diagram
101001
*
010010
Left
Shift
111011
*
Zero  CV*
exists
100100
110110
Left Shift
No CV*
101100
001000
ICV – 101001 OR
CVi – 001000
CV* 101001
State Diagram
101001
*
010010
111011
*
100100
101100
001000
010000
*
Zero  CV*
exists
110110
111001
ICV – 101001
CVi – 010000
CV* 111001
101001
*
*
010010
111011
100100
001000
*
010000
110110
111001
101100
Zero  CV*
exists
011000
ICV – 101001
CVi – 011000
CV* 111001
101001
*
*
010010
111011
100100
*
010000
*
001000
110110
101100
011000
111001
No CV*
110000
101001
*
*
010010
111011
100100
001000
*
*
010000
110110
101100
011000
111001
110000
No CV*
100000
101001
*
*
010010
111011
100100
001000
*
*
010000
110110
111001
101100
011000
110000
100000
000000
*
*
101001
*
010010
*
111011
100100
001000
*
010000
110110
111001
101100
011000
110000
*
100000
000000
*
101001
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
State Diagram
• From the above diagram, closed loops can be
identified as latency cycles.
• To find the latency corresponding to a loop, start
with any initial * count the number of states
before we encounter another * and reach back
to initial *.
101001
Latency = (3)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (1,3,3)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (4,3)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (1,6)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (1,7)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (4)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (6)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
101001
Latency = (7)
*
010010
*
111011
100100
001000
110110
101100
*
*
010000
111001
011000
110010
110000
*
100000
000000
*
State Diagram
• The state with all zeros has a self-loop which
corresponds to empty pipeline and it is possible
to wait for indefinite number of latency cycles of
the form (1,8), (1,9),(1,10) etc.
• Simple Cycle: latency cycle in which each state is
encountered only once.
• Complex Cycle: consists of more than one
simple cycle in it.
• It is enough to look for simple cycles
State Diagram
• In the above example, the cycle that offers MAL
is (1, 3, 3) (MAL = (1+3+3)/3 = 2.33)
• Thus we have,
MAL  maxN (i)  2
k
i 1
• A cycle arrived so is called greedy cycle, which
minimize latency between successive initiation
Modified State Diagram
• The state diagram becomes cumbersome for
longer ICVs.
• In modified state diagrams, we represent only
states obtained of initiations.
Modified State Diagram
• The procedure is as follows:
1. Start with the ICV
2. For each unprocessed state,
For each bit i in the CVi which is 0, do the
following:
a. Shift CVi left by i bits
b. Drop i leftmost bits
Modified State Diagram
c. Append zeros to right
d. Logically OR with ICV
e. If step(d) results in a new state then form a
new node for this state and join it with node
of CVi by an arc with a marking i. Join this
new node with node of ICV with an arc
having the marking ≥ d (length of ICV)
Modified State Diagram
101001
Modified State Diagram
101001
1
111011
i =1
ICV – 101001
CVi – 010010
CV* 111011
OR
Modified State Diagram
101001
≥6
1
111011
Modified State Diagram
101001
≥6
1
111011
i =3
ICV – 101001
CVi – 001000
CV* 101001
OR
Modified State Diagram
3
101001
≥6
1
111011
i = 3
Modified State Diagram
3
101001
≥6
i =4
1
111011
ICV – 101001
CVi – 010000
CV* 111001
OR
Modified State Diagram
3
101001
≥6
4
1
111011
111001
ICV – 101001
CVi – 010000
CV* 111001
OR
Modified State Diagram
3
101001
≥6
4
≥6
1
111011
111001
Modified State Diagram
3
≥6
101001
≥6
4
≥6
1
111011
111001
Modified State Diagram
3
≥6
101001
≥6
≥6
4
1
111011
111001
i =3
ICV – 101001
CVi – 011000
CV* 111001
OR
Modified State Diagram
3
≥6
101001
≥6
4
≥6
1
111011
3
111001
Modified State Diagram
3
≥6
101001
≥6
4
≥6
1
111011
3
111001
i =3
ICV – 101001
CVi – 001000
CV* 101001
OR
Modified State Diagram
3
≥6
101001
≥6
≥6
4
3
1
111011
3
111001
Modified State Diagram
3
≥6
101001
≥6
≥6
4
3
1
111011
3
111001
i =4
ICV – 101001
CVi – 010000
CV* 111001
OR
Modified State Diagram
3
≥6
101001
≥6
≥6
4
3
1
111011
3
111001
4