Virtual Memory Part 1
Li-Shiuan Peh
Computer Science & Artificial Intelligence Lab.
Massachusetts Institute of Technology
May 2, 2012
http://csg.csail.mit.edu/6.S078
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Virtual Memory Basics
machine
language
address
lw $t0, 32($s3)
ISA
virtual
address
Address
Mapping
0xABCDEFGH
32-bit ISA
lw $t0, 32($s3)
0xABCDEFGHIJKLMNOP
32-bit ISA
lw $t0, 32($s3)
0xABCDEFGHIJKLMNOP
64-bit ISA
May 2, 2012
physical
address
Physical
Memory
(Caches,
DRAM)
01HGFEDCB
1GB DRAM (230)
0xHGFEDCBA
4GB DRAM (232)
0xIHGFEDCBA
64GB DRAM (236)
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Virtual Memory Basics: Pages
machine
language
address
lw $t0, 32($s3)
ISA
virtual
address
0xABCDEFGH
Address
Mapping
physical
address
Physical
Memory
0xHGFEDFGH
Mapping individual addresses incurs too much overhead:
Let’s page it: Chunk address space!
machine
language
address
lw $t0, 32($s3)
May 2, 2012
ISA
virtual
address
Address
Mapping
(Page
Tables)
physical
address
Physical
Memory
Page Index:0xABCDE
0xHGFED
Page Offset:0xFGH
0xFGH
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Paged Memory Systems
Processor generated address can be
interpreted as a pair <page number, offset>
page number
offset
A page table contains the physical address
of the base of each page
0
1
2
3
Address Space
of User-1
1
0
0
1
2
3
3
Page Table
of User-1
2
Page tables make it possible to access and store
pages of a program non-contiguously
May 2, 2012
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Why Virtual Memory?
Illusion of a large, private, uniform store
OS
Protection & Privacy
several users, each with their private
address space and one or more
shared address spaces
page table  name space
useri
Swapping Store
Demand Paging
Primary
Provides the ability to run programs Memory
larger than the primary memory
Hides differences in machine
configurations
The price is address translation on
each memory reference
May 2, 2012
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VA
mapping
PageTbl
PA
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User 1
VA1
Page Table
User 2
Physical
Memory
Why Virtual Memory:
Reason #1: Protection & Privacy
So: Private Address Space per User
OS
pages
VA1
Page Table
User 3
VA1
Page Table
free
• Each user has a page table
• Page table contains an entry for each user page
May 2, 2012
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Address Translation &
Protection
Virtual Address
Virtual Page No. (VPN)
offset
Kernel/User Mode
Read/Write
Protection
Check
Address
Translation
Exception?
Physical Address
Physical Page No. (PPN)
offset
Every instruction access and data access needs address
translation and protection checks
May 2, 2012
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Why Virtual Memory:
Reason #2: Demand Paging (VM >> PM)
So: Page Table keeps track of disk vs. DRAM
Physical
Memory (DRAM)
Virtual
Addresses
Store 0x10
Page Table
0:
1:
Physical
Addresses
0:
1:
CPU
Load 0xf0
P-1:
N-1:
Disk
Page Faults: Page not in DRAM,
so, load from Disk to DRAM!
Linear Page Table: Implementing
Demand Paging and Protection
Page Table Entry (PTE)
contains:




A bit to indicate if a page
exists
PPN (physical page
number) for a memoryresident page
DPN (disk page number)
for a page on the disk
Status bits for protection
and usage
OS sets the Page Table
Base Register whenever
active user process
changes
PPN
PPN
DPN
PPN
Data word
Offset
DPN
PPN
PPN
DPN
DPN
VPN
DPN
PPN
PPN
PT Base Register
May 2, 2012
Data Pages
Page Table
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VPN
Offset
Virtual address
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Page Tables in Physical Memory:
1 memory access for translation +
1 memory access for actual access! +?
translation
PT User 1
VA1
User 1
VA1
User 2
May 2, 2012
access
PT User 2
Idea: cache the
address translation of
frequently used pages
– Translation Lookaside Buffer (TLB)
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A cache for address translations:
Translation Lookaside Buffers (TLB)
Cache address translations in TLB
TLB hit
 Single Cycle Translation
TLB miss
 Page Table Walk to find Page
Table Entry in DRAM, and refill into TLB
virtual address
VRWD
tag
hit?
May 2, 2012
VPN
offset
PPN
offset
PPN
physical address
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Virtual Memory: Translation +
Access
machine
language
address
ISA
virtual
address
Address
Mapping
physical
address
Virtual Memory
handles the
translation
and
filling DRAM
from Disk
May 2, 2012
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Physical
Memory
(Caches,
DRAM)
Physical Memory
handles the
access from DRAM
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Virtual Memory:
putting it all together
Virtual Address
hardware
hardware or software
software
TLB
Lookup
miss
hit
Protection
Check
Translation Page Table
Walk (DRAM)
miss!
 memory
Access
miss!
Page Fault
(OS loads page)
Where?
May 2, 2012
the page is
 memory
denied
Protection
Fault
Update TLB
SEGFAULT
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permitted
Physical
Address
(to cache
hierarchy)
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Handling a TLB Miss
Software (MIPS, Alpha)
TLB miss causes an exception and the operating system
walks the page tables and reloads TLB. A privileged
“untranslated” addressing mode used for walk
Hardware (SPARC v8, x86, PowerPC)
A memory management unit (MMU) walks the page
tables and reloads the TLB
May 2, 2012
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Page Fault Handler
When the referenced page is not in DRAM:



The missing page is located (or created)
It is brought in from disk, and page table is
updated
Another job may be run on the CPU while the
first job waits for the requested page to be read
from disk
If no free pages are left, a page is swapped out
approximate LRU replacement policy
Since it takes a long time (msecs) to transfer
a page, page faults are handled completely
in software (OS)

May 2, 2012
Untranslated addressing mode is essential to allow
kernel to access page tables
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Virtual memory +
processor + caches
PC
Inst
TLB
Inst.
Cache
TLB miss? Page Fault?
Protection violation?
May 2, 2012
D
Decode
E
+
M
Data
TLB
Data
Cache
W
TLB miss? Page Fault?
Protection violation?
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Physical or Virtual Address
Caches?
CPU
VA
PA
TLB
Physical
Cache
Primary
Memory
Alternative: place the cache before the TLB
VA
CPU
Virtual
Cache
TLB
PA
Primary
Memory (StrongARM)
one-step process in case of a hit (+)
cache needs to be flushed on a context switch unless
address space identifiers (ASIDs) included in tags (-)
aliasing problems due to the sharing of pages (-)
May 2, 2012
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Aliasing in Virtual-Address
Caches
VA1
Page Table
Data Pages
PA
VA2
Two virtual pages share
one physical page
Tag
Data
VA1
1st Copy of Data at PA
VA2
2nd Copy of Data at PA
Virtual cache can have two
copies of same physical data.
Writes to one copy not visible
to reads of other!
General Solution: Disallow aliases to coexist in cache
Software (i.e., OS) solution for direct-mapped cache
VAs of shared pages must agree in cache index bits
Hardware solution for direct-mapped cache
Cache size < Page size
May 2, 2012
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Let’s build!
Fetch
F
VA
Virtual
I$
p
c
f
r
Decode
D
Reg
Read
d
r
R
I$ miss (VA)
Execute
r
r
X
Memory
x
r
M
Writeback
m
r
W
VA
D$ miss (VA) Virtual
D$
TLB
PA
TLB miss
Physical
Page Table
L2$
Walker
Page Fault
DRAM (Page
Table)
Page Fault Exception
DRAM (Pages)
May 2, 2012
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