Getting Started with MPC560xB The Freescale Cup Steve Mihalik January 24, 2011 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Agenda – Getting Started with MPC560xB Time Topic 9:00 Overview 3 9:10 System Integration Unit – Pads, Simple I/O 11 9:20 Clocks 20 - Reference: Clock Management Unit 28 9:30 RUN Modes 34 PLL init, Mode Entry, Toggle Pin 10:00 Timed I/O – PWM, Counter, Input Capture 44 PWM & Counter 10:30 - Break - 10:45 Interrupts – 1 msec Task Scheduler 64 INTC & PIT 11:15 Analog to Digital Conversions (ADC) 73 ADC 11:45 Direct Memory Access (DMA) 86 Noon - Break - 12:15 Camera Interface - 12:40 Motor Interface - Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Slide # Exercise TM 2 MPC5607B Overview TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. MPC5607B (1.5MB Flash) System Integration Crossbar Masters Debug JTAG VReg PIT 4ch 32b PowerPCTM e200z0 Core Power Mgt Oscillator FMPLL Nexus 2+ DMA Interrupt Controller CROSSBAR SWITCH Memory Protection Unit (MPU) I/O Bridge 1.5M Flash 64K Data Flash Standby RAM 96K SRAM Boot Assist Module (BAM) Crossbar Slaves Communications I/O System eMIOS 64ch, 16 bit 6 FlexCAN 10 LINFlex 6 DSPI 1 I2C Up to 52 ch ADC 16x12bit, 36x10 Bit Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. CORE • Power Architecture e200z0 core running at 64MHz @ Ta=105C (48Mhz at 85oC Base) • VLE ISA instruction set for superior code density • Memory Protection Unit with 16 regions, 32byte granularity • 16 channel DMA controller MEMORY • 1.5M byte embedded program Flash • 64K byte embedded data Flash (for EE Emulation) • Up to 64MHz non-sequential access with 2WS • ECC-enabled array with error detect/correct • 96Kbyte SRAM (single cycle access, ECC-enabled) COMMUNICATIONS • 6x enhanced FlexCAN •10 x LINFlex • 6 x DSPI, 8-16 bits wide & chip selects • 1 x I²C ANALOG • Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution TIMED I/O • 16-bit eMIOS module, 64ch. OTHER • 32 Channel DMA Controller • Debug: Nexus 2+ • I/O: 5V I/O, high flexibility with selecting GPIO functionality • Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA* (TBD) • Boot Assist Module for production and bench programming TM 4 Data Organization in Memory Big Endian - Most Significant Byte 0 0x0 Big Endian – Least Significant Byte 0x6 31 32 A B C D 63 E F G H 0x8 0x10 MSb LSb 0 31 General Purpose Register (GPR) ► ► ► All MPC560xB instructions are either 16 or 32 bits wide. Power architecture is naturally Big Endian, but has switch for Little Endian Examples: Load word from address 0x0 loads the word “ABCD” Load half word from address 0x6 loads the half word “GH” Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 5 Start-Up Sequence 1. POR monitors internal voltage and de-asserts itself 2. Default clock is the 16MHz IRC 3. Boot configuration pins are sampled by the hardware possiblity to go into e.g. serial boot mode 4. Hardware checks reset configuration half word (RCHW) 5. If hardware finds a valid RCHW (0x5A) it reads the 32-bit word at offset 0x04 = address where Start-Up code is located (reset boot vector). • Device is put in static mode if no RCHW is found! Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM Flash and SRAM Overview RAM features: • • • • User transparent ECC encoding and decoding for byte, half word, and word accesses FLASH features: • • Up to 64k Data Flash on MPC560xB; same emulated EEPROM concept for most products of the MPC560xB family (sectorization; software compatibility; memory mapping) • 64-bit programming granularity (can change value from 10 only) • Read-while-write with Code and Data Flash or by RWW feature 32-bit ECC with single-bit correction (and visibility), double bit detection for data integrity ECC is checked on reads, calculated on writes CAUTION: ECC requires SRAM must be initialized by executing 32-bit write operations (32-bit word aligned) prior any read accesses • Done in initialization code before main Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Up to 1.5MB Code Flash (MPC5607B) • • Erase granularity is Sector size 64-bit ECC with single-bit correction (and visibility), double bit detection for data integrity TM Why did I get Reset? ► Destructive Reset Sources: • Power On Reset • Software Watchdog • 2.7V Low-voltage detected • 1.2 Low-voltage detected in Power Domain 1 • 1.2 Low-voltage detected in Power Domain 2 ► Status flag associated with a given ‘destructive’ reset event is set in the Destructive Event Status Register (RGM_DES) ► Functional Reset Sources: • External Reset • Code or Data Flash Fatal Error • 4.5V low-voltage detected • CMU clock freq higher/lower than reference • FXOSC freq. lower than reference • FMPLL failure • Checkstop reset • Software reset • Core reset • JTAG initiated reset ► Status flag associated with a given ‘functional’ reset event is set in the Functional Event Status Register (RGM_FES) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 8 Debug, Software & Tools RAppID: Rapid Application Initialization and Documentation ►RAppID PinWizard: • Wizard workflow to allocate pins to peripherals • Generates spreadsheet • Inputs to RAppID Init • Free utility ►RAppID Init: • Generates initialization code for startup from CRT0 • Generates interrupt handler code & framework • Has ability to define section map and place code into any desired section Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM Debug, Software & Tools RAppID PinWizard Screenshot Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 10 System Integration Unit Lite (SIUL) Pad Configuration, Simple I/O TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. ►Pad Control and IOMux configuration: Peripherals SIUL Introduction • Intended to configure the electrical parameters and I/O signal multiplexing of each pad; • may simplify PCB design by multiple alternate input / output functions ►General Purpose I/O (GPIO) ports: • Can write to GPIO data output pin or port • Can read GPIO data input pin or port ►External • interrupt management Allows the enabling and configuration (such as filtering window, edge and mask setting) of digital glitch filters on each external interrupt pin Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM Peripherals SIUL Pad Control and IOMux configuration overview ►Pad Control is managed through Pad Configuration Registers (PCRs) ►IOMux configuration is managed through: • PCR Registers (output functionalities) • PSMI Registers (input functionalities) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM SIUL Pad Control and IOMux config 0 R W Reset 0 1 2 SMC APC 0 0 Pad Configuration PCRn.SMC Reg. (PCR) IP 1 0 4 5 6 7 PA OBE IBE 0 0 1 8 9 10 11 0 0 0 0 PAD n PCRn.OBE PCRn.PA 14 15 SRC WPE WPS 0 0 0 PCRn.WPS PCRn.ODE ADC ch #… 0 13 PCRn.WPE a) b) PCRn.APC IP 3 12 ODE SoC Safe Mode IP 2 IP 4 3 PCRn.SRC PCRn.IBE PAD m Pad Select Multiplexed Inputs (PSMI) reg. IP a PSMI.PADSEL Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 14 Peripherals SIUL Pad Control and IOMux configuration 2/4 Alternate functions are chosen by PCR.PA bitfields: PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11-> AF3. This is intended to select the output functions; For input functions, PCR.IBE bit must be written to ‘1’, regardless of the values selected in PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “--”. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 15 Peripherals PSMI SIUL Pad Control and IOMux configuration 3/4 PAD j PAD k IP “n+1” PAD l PAD m PSMIn_n+3 Register 0 R W 1 0 2 0 3 0 4…7 0 PADSELn 8 9 0 0 10 11 0 0 12 … 15 PADSEL(n+1) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 16 17 18 19 0 0 0 0 20 … 23 PADSEL(n+2) 24 25 26 27 0 0 0 0 28 … 31 PADSEL(n+3) TM 16 Peripherals SIUL Pad Control and IOMux configuration 4/4 0 R W 1 0 2 0 3 0 4…7 0 PADSELn 8 9 0 10 11 0 0 0 12 … 15 PADSEL(n+1) 16 17 18 19 0 0 0 0 20 … 23 PADSEL(n+2) 24 25 26 27 0 0 0 0 28 … 31 PADSEL(n+3) ►Different pads can be chosen as possible inputs for a certain peripheral function. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 17 SIUL Peripherals SIUL GPIO Functionality PAD Control PCR Regs PSMI Regs GPIO functionality Data IOMux & Pad Inputs PADs Ext. Interrupt Mgmt • Interrupt config Interrupt Controller • Glitch filter Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 18 SIUL General Purpose I/O ►GPIO • On individual base (R/W access to a single GPIO); • pads can be managed two ways: Access is done on a byte basis On port base (parallel access). Code example for writing to individual GPIO pin: SIU.PCR[68].B.PA = 0; /* Port E4 pin: Pad Assignment is GPIO */ SIU.PCR[68].B.OBE = 1; /* Port E4 pin: Output Buffer Enabled */ SIU.GPDO[68].R = 1; /* Port E4 pin: write 1 to Data Output */ ►Ports • • • accesses can be: Data Read: 32-bit, 16-bit or 8-bit accesses Data Write: 32-bit, 16-bit or 8-bit (only if not masked access) Masked Access: This mechanism allows support for port accesses or for bit manipulation without the need to use read-modify-write operations Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 19 Clocks TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Platform Overview – Clocks ►Clock Sources for Code Execution, System • 4-16 MHz External Crystal/Oscillator -> FXOSC Clock (sysclk) Input to phase lock loop (FMPLL) to generate up to 64 MHz sysclk FMPLL has frequency modulation option to reduce EMC • 16 MHz Internal RC Oscillator -> FIRC Default system clock after Reset Trimable ► Low Power Clock Sources • 32 KHz External Crystal/Oscillator -> SXOSC Low power oscillator Dedicated for RTC/API • 128 KHz Internal RC Oscillator -> SIRC Dedicated for RTC/API and watchdog Trimable Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 21 Platform overview – Clocks • Clock Monitor Unit (CMU) for • PLL clock monitoring : detect if PLL leaves an upper or lower frequency boundary • Crystal clock monitoring : monitors the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV[1:0] of CMU_CSR register. • Frequency meter : measure the frequency of one clock source versus a reference clock. • CMU “event” (failure) will cause reset, SAFE mode request or interrupt request Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 22 Platform overview – Clocks MPC560xB CGM Clocking Structure FXOSC 4-16MHz FIRC 16MHz div 1 to 32 FXOSC_DIV FIRC_DIV div 1 to 32 SYSCLK System Clock Selector (ME) FMPLL FIRC FXOSC 32KHz 128KHz CMU SXOSC SIRC SXOSC 32KHz div 1 to 32 SIRC 128KHz div 1 to 32 RESET SAFE INT Core Platform div 1 to 16 Peripheral Set 1 div 1 to 16 Peripheral Set 2 div 1 to 16 Peripheral Set 3 FIRC_DIV SXOSC_DIV API / RTC SIRC_DIV FXOSC FIRC FMPLL SWT (Watchdog) CLKOUT Selector Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. div 1/2/4/8 CLOCK OUT TM 23 Platform overview – Clocks MPC560xB CGM System Clock ►Provides the clock (divided or not) to the Core/Peripherals ►Selected by ME_XXX_MC register (XXX is desired mode) in the Mode Entry (ME) module SYSCLK FXOSC Core Platform FXOSC_DIV FIRC FIRC_DIV System Clock Selector (ME) FMPLL Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Enable & div 1 to 16 Peripheral Set 1 Enable & div 1 to 16 Peripheral Set 2 Enable & div 1 to 16 Peripheral Set 3 TM 24 Platform overview – Clocks MPC560xB CGM System Clock Divider Configuration Register Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 All LINFlex modules All FlexCAN modules All eMIOS modules I2C module All DSPI modules CTUL ADC DEx: DIVx: Peripheral Set x Divider Enable (Default value 1 = ON) Peripheral Set x Divider x Division Value (1..15) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 25 Platform overview – Clocks MPC560xB CGM Output Clock Description ►Clock output on the GPIO[0] (PA[0]) pin FXOSC FIRC FMPLL CLKOUT Selector SELDIV: SELCTL: div 1/2/4/8 CLOCK OUT (GPIO[0]) division by 1, 2, 4, 8 clock source (XOSC, FIRC, PLL) selection Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 26 CGM FMPLL Normal mode The PLL output clock frequency derives from the relation: FMPLL = Input divider 1..15 4 (FXOSC x NDIV) (IDF x ODF) Output divider 2/4/8/16 4MHz 128MHz FMPLL 2 16MHz 64MHz 32 Loop divider 32..96 Example: FXOSC = 16MHz FMPLL = 64MHz NDIV = 4 * IDF * ODF NDIV = 32 , IDF = 4 , ODF = 2 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 27 CMU Ref.: Clock Monitor Unit Tasks ►The first task of the CMU is to permanently supervise the integrity of the various product’s clock sources, e.g. FXOSC or FMPLL, if either • • FXOSC clock frequency lower than FIRC / 2n PLL clock frequency upper or lower frequency boundaries defined in CMU registers ►If an integrity problem occurs, the Mode Entry module is notified in order to switch to SAFE mode with FIRC as clock source. ►The second task is frequency measurement. It allows to measure the deviation of a clock (FIRC, SIRC or SXOSC ) by measuring its frequency versus FXOSC as reference clock. • • Can be used to improve IRC calibration Can be used for Real Time Counter precision Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 28 Crystal Clock Monitor CMU Ref.: ►Crystal clock monitor is active only when ME provides the info that FXOSC is valid ►If FXOSC < FIRC / 2RCDIV (CMU_CSR[RCDIV] bits), then • • an event pending bit CMU_ISR[OLRI] is set. a failure event is signaled to the RGM which in turn can generate a RESET, transition to SAFE mode, or generate an interrupt request FXOSC Failure FXOSC FIRC FXOSC supervisor FFXOSC < FFIRC / 2 RGM, ME RCDIV FXOSC stable/unstable CMU_ISR register Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 29 CMU Ref.: Crystal Clock Monitor Reset Default Values ►CAUTION: Before enabling crystal clock input in a mode configuration, verify the proper compare frequency divider. • MPC560xB, MPC560xS: reset default RCDIV = 3, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 8 = 2 MHz • MPC560xP: reset default RCDIV = 0, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 1 = 16 MHz Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 30 CMU Ref.: Crystal Clock Monitor Event Behavior ►Oscillator Less than Reference event occurs when the FXOSC appears too slow and sets: ► CMU_ISR[OLRI] • ► No interrupt or other automatic action can be generated – just sets the bit RGM_FES[F_CMU_OLR] • Action taken is per table below: Functional Event Reset Disable: FXOSC freq. lower than reference Functional Event Alternate Request: Alternate Request for FXOSC freq. lower than reference RGM_FERD [D_CMU_OLR] RGM_FEAR [AR_CMU_OLR] 0 (reset default) - 1 0 (reset default) 1 1 Action Reset sequence SAFE mode request Interrupt request – INTC #56 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM CMU Ref.: ►FMPLL FMPLL Monitor – Frequency Range monitoring is enabled at CMU_CSR(CME) ►Monitoring is active only when ME provides the info that FMPLL is valid. ►Depending • • on the following conditions If FFMPLL is lower than HLREF[11:0] bits in CMU_LFREFR If FFMPLL is higher than HFREF[11:0] bits in CMU_HFREFR Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 32 CMU Ref.: ►Then • • FMPLL Monitor – Failure Behaviour for each matching: a dedicated event pending bit in CMU_ISR is set. a failure event is output to the RGM & ME which can generate a transition to SAFE mode, an interrupt or a reset sequence. CMU_HFREF register FMPLL Fpll > LHREF threshold FIRC Fpll < LFREF threshold ME, RGM FMPLL Failure CMU_LFREF register FMPLL stable/unstable CMU_ISR register Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 33 RUN Modes Introduction TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Use Case: Conserving Power While Software Runs (1 of 2) ►Software • runs one of the three following tasks: Analog Monitor Uses ADC to look for particular voltages on inputs Only requires 16 MHz FIRC, which is also sysclk If analog input measurements meet a criteria, software transitions to the communication task • Communication Uses FlexCAN_0, FlexCAN_1 to transmit analog data and receive response Only requires FXOSC, which is also sysclk If response is positive, software transitions to the whole chip task • Whole Chip Requires all peripherals active Sysclk = 64MHz FMPLL, which also requires FXOSC Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 35 Use Case: Conserving Power While Software Runs (2 of 2) Run Mode sysclk Clock Sources Req’d FIRC XOSC FMPLL Mode Configuration RUN0: AnalogMon FIRC RUN1: Comm XOSC X RUN2: WholeChip FMPLL X Peripherals Peripheral Control Reg. # ADC 32 FlexCAN_0, 1 16, 17 SIU 68 All others Other #’s Peripherals Requiring Enabled Clock X Peripheral Configuration ADC, SIU FlexCAN_0, FlexCAN_1, SIU X All Modes with Enabled Clock RUN0 RUN1 X X Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. RUN2 RUN3 RUN Mode Peripheral Configuration X Run PC0 X X Run PC1 X X Run PC2 X Run PC3 TM 36 Mode Overview ►The Mode Entry Module (MC_ME) provides SYSTEM modes and USER modes : • • SYSTEM: RESET, DRUN (Default RUN), SAFE and TEST USER: RUN(0..3), HALT, STOP and STANDBY ►For • • • • • each mode the following parameters are configured/controlled System clock sources (ON/OFF) System clock source selection Flash power mode (ON, low power, power down) Pad output driver state (For low power modes - can disable Pad Output drivers, enabling high impedance mode) Peripherals’ clock (gated/clocked) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 37 Device USER Modes - Diagram MODES LOW POWER MODES SYSTEM MODES Recoverable HW failure SW request RUN 0 SAFE HALT RUN 1 RESET DRUN STOP RUN 3 Non recoverable HW failure TEST STANDBY HW triggered transition SW triggered transition Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 38 ME_xxx_MC - Mode Configuration Registers • Each mode has a Mode Configuration register. • • Example: ME_DRUN_MC Key RUN mode configurations are circled: 0 1 2 3 4 5 6 7 reserved 16 17 18 19 20 21 22 23 reserved • PDO: Disable pad outputs (put in hi Z) • MVRON: control VREG on/off • CFLAON/DFLAON: control code / data flash module 8 9 PDO reserved 24 25 PLL ON 11 10 MVR ON 26 27 OSC ON IRC ON 12 13 DFLAON 28 14 15 CFLAON 29 30 31 SYSCLK • PLLON: control PLL on/off • OSCON: control XOSC on/off • IRCON: control IRC16M on/off • SYSCLK: select system clock Normal Low Power Power Down Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 39 Mode Configurations Example • It is useful to keep a table of mode configurations used. • Example below uses two USER modes. (Per AN2865 rev 4) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 40 Peripheral Clock Gating Control • • Each peripheral can be associated with a particular clock gating policy The policy is determined by two groups of peripheral configuration registers: • ME_RUN_PC0:7 for RUN modes • ME_LP_PC0:7 for Low Power modes • Clocks to peripherals are gated off unless enabled for that mode • Example (per AN2865 rev 4): Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 41 MC_ME Peripheral Configuration Registers RUN Modes Defines a selection of 8 possible RUN mode configurations for a peripheral Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 42 Device Start-up: MC_ME Peripheral Control Registers For each peripheral, there is a ME_PCTLx register to control clock gating to that peripheral: - selects one of the 8 Run peripheral set configurations - selects one of the 8 Low Power peripheral set configurations - enables/disables freezing the clock during debug Peripheral 143 Peripheral 3 Peripheral 2 Peripheral 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 43 Mode Entry: SW and HW Transitions ►Software • • • • • handled transition A transition is requested writing a key protected sequence in ME_MCTL Mode Entry configures the modules according to the ME_xxx_MC register of the target mode Once all modules are ready the new mode is entered Transition completion signalling: status bit/interrupt Note: Modification of a ME_xxx_MC register (even the current one) is taken into account on next mode “xxx” entry ►Hardware • • • triggered transition Exit from low power mode SAFE transition caused by HW failure RESET transition caused by HW failure Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 44 ► Review of Key Points ► RUN mode configurations allow 1. 2. 3. Enabling/disabling system clock sources Selecting appropriate system clock Gating clocks to peripherals ► Peripheral clocks can be divided as needed on a set basis ► Example PLL: Initializing System Clock Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 45 Exercise: Initialize PLL & RUN Mode, Write GPIO Output 1. Open existing CodeWarrior Project, “PLL-sysclk” 1. Navigate to the PLL-sysclk project for MPC560xB. Example path: C: \ Program Files \ Freescale \ CW for MPC55xx and MPC56xx 2.7 \ (CodeWarrior_Examples) \ 560xB-CW \ PLL-sysclk 2. Double click on the project file “PLL-sysclk.mcp” to open it in CodeWarrior 2. Compile and link RAM project 1. Either a) click: Project – Make – or-- b) click on the make icon 3. Download to target 1. Connect EVB to PC with USB cable 2. Either click: Project – Debug, or, click on the Debug icon 3. Click the “Connect” button 4. Type “gotil main” in the Status Window 4. Initialize registers to turn on LED1 on target board 1. Click the “REG” button at the top 2. Click “SIUL System Integration Unit Lite” 3. Set bit fields for a GPIO output (PCR68: PA=1, OBE=1; GPDO68: PDO=1) 4. Exit register windows then open again to validate the register was altered Are registers still shown as modified? Execute thru initModesAndClock &re-try. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 46 Timed I/O (Watchdog, PIT & eMIOS) TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Watchdog Timer – Regular Mode Servicing ► To prevent the watchdog from interrupting or resetting, the following sequence must be performed before a timeout period: 1. Write 0xA602 to the SWT_SR 2. Write 0xB480 to the SWT_SR Note: other instructions, such as an ISR, can occur between above writes Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 48 Programmable Interrupt Timer (PIT) Features ► Clocked by system clock ► 32-bit counter ► Independent timeout periods for each timer ► Timer can generate interrupt/DMA request, ADC conversion PIT # Interrupt Request DMA Request Peripheral Trigger 0 YES YES NO 1 YES YES NO 2 YES NO 10-bit ADC 3 YES NO CTU ch23 (can trigger ADC) 4 YES YES NO 5 YES YES NO 6 YES NO 12-bit ADC 7 YES NO CTU ch55 (can trigger ADC) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM eMIOS260 Introduction • Provides various modes to generate or measure timed event signals. • 24 to 56 Channels • One new channel mode featuring lighting applications, OPWMT • All other channel modes are subset of the unified channel structure on previous eMIOS. • Consistent user interface with previous eMIOS implementation. IRC 16M OSC 4-16M Debug e200z0h Core IRC 128K Integer Execution Unit OSC 32K General Purpose Registers (32 x 32-bit) PLL Multiply Unit Branch Unit VREG Instruction Unit VLE Load/Store Unit (C)JTAG INTC Crossbar Switch (XBAR) Memory Protection Unit (MPU) 8 regions FLASH Controller RAM Controller Code Flash (ECC) SRAM (ECC) Peripheral Bridge Data FLASH (ECC) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. DSPI 2-4 STM 4 ch SWT eMIOS-lite 24 – 56 ch FlexCAN 1-6 PIT 6 ch I2C 1 BCTU LINFlex 3-8 API/RTC SIU ADC10 16 – 57 ch TM 50 eMIOS Channel Modes Type Abbr. Channel Mode Counter MCB Modulus Counter (up or up/down) Input SAIC Single Action Input Capture IPWM Input Pulse Width Measurement IPM Input Period Measurement SAOC Single Action Output Compare DAOC Double Action Output Compare OPWMB Output Pulse Width Modulation OPWMT Output Pulse Width Modulation with Trigger OPWFMB Output Pulse Width & Frequency Modulation Output OPWMCB Center aligned Output Pulse Width Modulation with dead time Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 51 Example: MPC5604B eMIOS channel configuration Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 52 MPC5605/6/7B Block Structure EMIOS Blocks – EMIOS_A and EMIOS_B ► Each Block contains 32 Unified Channels ► Common System Clock Devider ► Separate Global Prescaler ►2 System Clock (/1,2,4,8,16) Default /1 EMIOS_B EMIOS_A Channel 0 Channel 0 Prescaler (/1, 2, 3, 4) Prescaler (/1, 2, 3, 4) Global Prescaler (/1, 2, 3, … 256) Global Prescaler (/1, 2, 3, … 256) Channel 31 Prescaler (/1, 2, 3, 4) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Channel 31 Prescaler (/1, 2, 3, 4) TM 53 eMIOS260 Unified Channel Features • Selectable time base for each counter bus • Programmable Clock Prescaler • Double buffered data registers and comparators • State Machine (with mode control) • Programmable as input or output: - • Input Edge Detect as rising, falling or toggle. Programmable digital input filter Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 54 eMIOS260 Double Buffered A and B Registers ►A and B data registers are double buffered to provide a mechanism for safe update of the A and B register values • This also enables very small pulse / period generation or measurement since updates can happen in current period ► The channel A user registers are an address mapped link to either the A1 or A2 register (determined automatically by the mode of the unified channel). • For output modes, data is typically written to the A2 register • For input capture modes, data is latched into either A1 or A2 depending on mode. • All of this is transparent to the user Comparator A Note – Same applies to B set registers as well! Register A1 UCAn Register (User Accessible) Register A2 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 55 Peripherals EMIOS counter buses UC[27] ►The MPC560xB family has 5 shared counter busses allowing common counter bus timing across multiple channels • • • • • Counter Bus A is shared with all channels and driven from channel 23 Counter bus B is shared with channels 0 to 7 and driven from channel 0 Counter bus C is shared with channels 8 to 15 and driven from channel 8 Counter bus D is shared with channels 16 to 23 and driven from channel 16 Counter bus E is shared with channels 24 to 27 and driven from channel 24 UC[24] Counter Bus E UC[23] Counter Bus A UC[16] Counter Bus D UC[15] UC[8] UC[7] UC[0] Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Counter Bus C Counter Bus B TM 56 Peripherals EMIOS - Single Action Input Capture Returns the value of the counter bus on an edge match of an input signal . - Can use Internal or Modulus counter - Can match on Rising, Falling or Toggle determined by state of EDPOL, EDSEL Edge detect Edge detect Edge detect input signal selected counter bus $000500 $001000 $001100 $001250 $001525 $0016A0 FLAG pin / register A2 (captured) $xxxxxx value $001000 $001250 $0016A0 Notes: • When edge is detected, flag is set and counter bus value is captured in register A2. User reads this value from UCA[n] register. • UCB[n] = Cleared and cannot be written Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 57 Peripherals EMIOS - Modulus Counter Buffer Mode – UP Counter Generates a time base which can be shared with other channels through the internal counter buses - Can use Internal or External (input channel pin) counter Internal Counter (UCCNTn) 0x001000 0x000800 0x000001 FLAG pin / register A1 value $001000 $001000 A2 value $001000 A1 match $001000 $000800 $000800 write into A2 A1 match update of A1 $000800 A1 match Notes: • On a comparator A match, FLAG is set and the internal counter is set to value $1. • Allowing smooth transitions, a change of the A2 register makes the A1 register be updated when the internal counter reaches the value $1. • Caution – If when entering MCB mode the internal counter value is upper than register UCA[n] value, then it will wrap at the maximum counter value ($FFFFFF) before matching A1. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 58 Peripherals EMIOS - OPWMFMB Generates a simple output PWM signal - Requires INTERNAL Counter - EDPOL allows selection between active HIGH or active LOW duty cycle . output flip-flop EDPOL=0 output flip-flop EDPOL=1 Selected counter bus 0x001000 0x000800 0x000200 B1 value $001000 A1 value $000200 $001000 $000200 $000200 A2 value $000200 A1 match $001000 B1 match $000800 write into A2 A1 match $000800 B1 match update of A1 $001000 $000800 A1 match B1 match Notes: • Duty Cycle = UCA[n] (A1) + 1, Period = UCB[n] (B1) + 1 • On Comparator A1 match, Output pin is set to value of EDPOL • On Comparator B1 match, Output pin is set to complement of EDPOL and Internal counter is reset • The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle. • FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 59 Peripherals EMIOS - OPWMB Generates a simple output PWM signal - Can use Internal or Modulus counter - EDPOL allows selection between active HIGH or active LOW duty cycle. output flip-flop EDPOL=1 Selected counter bus 0x001000 0x000800 0x000600 0x000400 0x000200 B1 value $000800 $000800 B2 value $000800 $000600 $000600 $000600 A1 value $000200 $000200 $000400 $000200 A2 value $000200 A1 match $000800 $000400 $000400 B1 match write into A2 & B2 A1 match update of A1 & B1 B1 match Notes: • Write UCA[n] (A1) with Leading Edge. Write UCB[n] (B1) with trailing edge • On Comparator A1 match, Output pin is set to value of EDPOL • On Comparator B1 match, Output pin is set to complement of EDPOL • The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle. • FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 60 Peripherals EMIOS - OPWMT Generates a PWM signal with a fixed offset and a trigger signal - Intended to be used with other channels in the same mode with shared common time base This mode is particularly useful in the generation of lighting PWM control signals. output flip-flop EDPOL=1 FLAG pin / register Selected counter bus 0x001000 0x000800 0x000600 0x000400 0x000200 B1 value $000800 $000800 $000800 B2 value $000800 A1 $000600 $000600 A1 value $000200 $000200 A2 value $000400 $000600 $000200 $000400 A2 $000200 $000400 B1 A1 A2 write into $000400 B1 Update A1 A2 B1 match match match match match match match of B2 match match B2 Notes: • A1[n] defines the Leading Edge, B1[n] the trailing edge, A2[n] the generation of a FLAG event • On Comparator A1 match, Output pin is set to value of EDPOL • On comparator A2 match, FLAG is set (and can allow to synchronize with other events, ie. AD conversion) • On Comparator B1 match, Output pin is set to complement of EDPOL • The transfers from register B2[n] to B1[n] is performed at every match of register A1 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 61 Peripherals EMIOS - Programmable Input Filter • Filter Consists of a 5 bit programmable upcounter, clocked by either the channel or peripheral set clock (defined by FCK) FCK Prescaled Channel CLK • Input signal is synchronised to system clock. • When the synchroniser output changes state, the counter starts counting up CLK If the synchroniser state remains stable for the desired number of selected clocks, the counter overflows on next high clock edge, counter resets and filter output changes Clock IF2 IF1 IF0 Filter Out 5-Bit Up Counter Peripheral Set CLK Synchroniser PIN • IF3 Filter can be set to trigger after 2,4,8 or 16 clocks (or bypassed) 1 1 1 Start Start Start 2 3 4 1 Overflow Start 2 1 1 Start Start Input Sig IF[0:3] = 0010 5-bit counter Filter Out Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 62 ► Review of Key Points ► eMIOS channels can be configured for desired timing function • • • ► Global, local or individual channel time bases • • ► Input functions: SAIC, IPM, IPWM, GPIO Output functions: DAOC, OPWM, OPWMT, OPWMC, OPWFM, GPIO Modulus counter Input functions can share common time base Output functions can be synchronized Example eMIOS OPWM, Modulus Counter Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 63 Interrupts TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. MPC5604B Interrupt Structure ► ► Interrupt Requests from Interrupt Controller (INTC) Interrupt Requests from Core Exceptions (e200z0) 8 Software 3 MCM 2 Wdog & clock Critical Input 4 STM 2 RTI/API Machine Check 5 SIU & WPU 5 Magic Carpet 6 PIT 3 ADC Data Storage INTC in Software Vector Mode 54 CAN 1 IIC 28 eMIOS Instruction Storage External Input Alignment CPU Interrupt Program System Call Debug 15 DSPI CPU Core 12 LIN INTC interrupts are assigned one of 16 priority levels, enabling premption Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 65 Interrupt Behavior Interrupt is recognized 1. 2. 3. 4. Hardware context switch: Stores address of next instruction or instruction causing interrupt • Stored into special purpose reg. Save & Restore Reg 0 (SRR0) Stores Machine State (MSR bits 16:31): • Stored into special purpose reg. Save & Restore Reg 1 (SRR1) Alters Machine State: All bits are cleared in MSR except ME Alters Instruction Pointer: points to unique interrupt vector Software Interrupt handler (at interrupt vector) • Execute your handler code, including save/restore registers • Last instruction, rfi*, (return from interrupt): - Restores MSR bits 16:31 from SRR1 - Restores instruction pointer from SRR0 * “Critical” and “debug” interrupts use rcfi and rdfi instruction instead of rfi. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 66 e200z0 Core Interrupts ►External input Exception (EE) ► enables/disables all interrupts from the interrupt controller. ►Each exception type can normally be individually enabled or disabled in the Machine State Register (MSR) Core Interrupt Type IVOR # IVPR Offset Critical Input IVOR 0 0x000 Machine Check IVOR 1 0x010 Data Storage IVOR 2 0x020 Instruction Storage IVOR 3 0x030 External Input IVOR 4 0x040 Alignment IVOR 5 0x050 Program IVOR 6 0x060 System Call IVOR 8 0x080 Debug IVOR 15 0x0E0 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM INTC: INTC’s IRQ n taken MPC560x Software & Hardware Vector Modes Address Instructions IVPR0:19 + 0x40 prolog Software Vector Mode Address Core’s VTBA ISR Vector Table2 ISR_0 address Address (including using IACKR to get vector then bl ISR_n) ISR_1 address epilog … … ISR_n address Handler Branch Table Instructions1 IVPR0:19 + 0x800 b handler_0 IVPR0:19 + 0x804 b handler_1 IVPR0:19 + 0x808 b handler_2 … INTC’s IRQ n taken IVPR0:19 + 0x0800 + n(0x4) b handler_n … IVPR0:19 + 0x0C8C b handler_286 ISR_n ISR ► ISR_286 handler_0 . . . Notes: 1. “b handler_n” handler_n instruction is . technically part of the . handlers. . 2. ISR Vector Table alignment in software handler_291 vector mode assumes INTC_MCR[VTES]=0. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. ISR ► ISR_286 address Hardware Vector Mode ISR_0 ISR prolog ISR epilog prolog ISR epilog prolog ISR epilog TM 68 Interrupt Vector Core Interrupts & INTC Software Vector Mode Interrupts • The interrupt vector address is composed of two components: Vector base address used as a prefix (special purpose register IVPR bits 0:19) A fixed offset base on the IVOR # • Each interrupt vector address would contain your branch instruction to that handler. • Example: Core interrupt IVOR 4 taken: Base Address IVPR Jump to address in Prefix Register (IVPR) + offset of 0x40 for IVOR4 IVOR0 IVOR1 IVOR2 IVOR3 IVOR4 Execute branch to IVOR4 handler IVOR15 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 69 Interrupt controller INTC Preemption ► ► Interrupt sources are assigned 1 of 16 priority levels • 15 is highest priority, 0 is lowest • Each interrupt source’s priority is specified in its Priority Select Register (8 bits wide), INTC_PSRx The Interrupt Controller records the current interrupt’s priority. - The current priority is in the Current Priority Register, INTC_CPR - Only interrupts with a priority higher than current priority can be recognized, allowing preemption. ► Preempted priorities are automatically pushed/popped to/from a LIFO in the interrupt controller. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 70 ► Review of Key Points ► INTC Software Vector Mode • • ► INTC Hardware Vector Mode • • ► INTC Interrupt vector is fetched by software Memory efficient due to common prologue, epilogue INTC Interrupt vector is automatically fetched by hardware Saves some time Example INTC SW mode with VLE, or INTC HW mode with VLE Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 71 ADC, CTU TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. ADC: Overview Feature MPC5604B MPC5605/6/7B Resolution 10 bit ADC 10 bit ADC & 12 bit ADC Number of channels 28 or 36 channels Up to 48 channels: • 19 12-bit, • 29 10-bit (19 channels can be shared) Add’l channels w. mux. Up to 28 Up to 44 Accuracy (TUE) 2 LSB internal 3 LSB external (mux.) Minimum conversion time 1 usec 1 usec Input range 0 – 5V 0 – 5V Output Dedicated result registers Dedicated result registers Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 73 ADC: Signal Name (per Table 2-3) MPC5607B Mapping: Signals, ADC, CTU ADC Channel # (per Fig 23-1) CTU EVTCFTRx [CHANNEL_VALUE] * Not on MPC5604B/C ADC0 ADC1* ANP 0:15* 0:15 0:15 0:15 - - - - ANS 0:7 32:39 32:39 32:39 ANS 8:27* 40:59 - - - - ANX 0, MA 0:7 64:71 - 32:39 ANX 1, MA 0:7 72:79 - 40:47 ANX 2, MA 0:7 80:87 - 48:55 ANX 3, MA 0:7 88:95 - 56:63 40:59 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 74 ADC: MPC560xB Trigger Options Option Selected Channels Trigger Initiation Trigger Enables Normal Multiple, as selected in NCMR (Normal Conversion Mask Register) • Software sets NSTART bit None Multiple, as selected in JCMR (inJected Conversion Mask Register) • Software sets JSTART bit or • PIT2 expires • Single, as selected in CTU_EVTCFGRx [CHANNEL_VALUE] • •CTU_EVTCFGRx •Scan or •One shot modes Injected •One shot mode only Cross Trigger Unit (CTU) PIT3, • PIT7 or • eMIOS channels (up to 46) Software: none • PIT2: PIT2 configured and MCR[JTRGEN] •MCR[CTUEN & ADC_SEL] • EMIOS_CHx_CCR [DMA, FEN] Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 75 ADC: AIN0 AIN1 Block Diagram ADC data registers SAMPLE & HOLD ANALOG MUX 10 bit Converter D0 D1 . SUCCESSIVE APPROXIMATION A/D CONVERTER AINx . ANALOG MUX . D94 End of conversion End of injection Threshold Violation Interrupts D95 EMIOS Timer channels Cross triggering Unit ADC_PRE-EMPTS Trigger event for injected conversion The CTU will automatically signal the channel to be converted by hardware Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. ADC_CONTROL Analog watchdog TM 76 ADC: Conversion Modes Normal conversion mode one–shot mode or scan mode possible Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 77 ADC: Programmable Analog Watchdog ►4 to 6 Analog Watchdogs can monitor any ADC channel ► Number depends on device implementation ►Programmable UPPER and LOWER threshold ►Dedicated ADC (WD) Interrupt on UPPER and/or LOWER threshold violation ►Can be used in a lighting application to trim SMARTMOS devices to prolong LED life • Use EMIOS (OPWMT mode) -> CTU -> ADC to continually monitor LED voltage • 0% CPU loading • Only use CPU in event of ADC watchdog interrupt Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM ADC Channel Masks ►Individual ► ► channel mask bits enable: Normal conversion Injected conversion Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 79 ADC – Channel Data Registers ►Each channel has a data register containing: ►VALID indication of new value written (cleared when read) ►OVERWrite data indication that previous conversion data is overwritten by a new conversion ►RESULT indication of conversion mode: normal, injected, CTU ►CDATA with channel’s converted data value Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 80 ADC Interrupts ►Each ADC converter has two interrupt vectors to the INTC: ►ADC_EOC: ADC End of conversion • • • • • End of (normal) chain conversion End of (normal) channel conversion (channels selected separately) End of injected chain conversion End of injected channel conversion End of CTU conversion ►ADC_WD: • • ADC watchdog Watchdog0:3 or 5 high thresholds exceeded Watchdog0:3 or 5 low thresholds exceeded Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 81 CTU: Purpose ►The Cross Triggering Unit Lite on the MPC560xB family is a link between timers (eMIOS or PIT) and the ADC ►The CTU “Lite” (as on MPC560xB) automatically transforms timer events into ADC conversions without main CPU intervention ►The real-time behavior (synchronization) between timer events and ADC conversions is guaranteed Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 82 CTU: MPC54605/6/7B Trigger Events eMIOS A0 Ch0 Trig eMIOS A22 Ch22 Trig eMIOS A24 Ch24 Trig ADC Control eMIOS eMIOS A31 Ch31 Trig ADC Trigger eMIOS B0 Ch32 Trig eMIOS B22 Ch54 Trig ADC Done CTU 10-bit ADC Injection trigger eMIOS B24 Ch56 Trig ADC Control eMIOS B31 Ch63 Trig PIT3 Ch23 Trig PIT7 Ch55 Trig PIT ADC Trigger ADC Done PIT2 Injection trigger PIT6 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 12-bit ADC TM 83 PWM & Diagnosis Timing tchd tirsd Calculations: 200Hz 5ms Period MDDC = 8% of 5ms = 400us tdwmin = MDDC – tirsd tdwmin = 400us -300us = 100us tdw ADC 200Hz channels (n+1) Ch 0 tirsd tdw ADC Ch 1 Ch n-1 Ch n Definitions: PWM 200Hz (0.35% resolution, xybit) MDDC: 8% (Min Diag Duty Cycle: For Duty cycles <8% no diagnosis is required) tchd: 1ms (Channel Delay to control inrush current as well as EMC on ECU level) tirsd: 300us (Inrush Delay to ensure ADC measurement takes place once current is stable) tdwmin: 100us (Diagnosis Window = Min. Diag. Duty Cycle – Inrush Delay) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 84 eMIOS OPWMT Mode: Allows Match A2 Match A1 Match B1 Period B1 C1 A1 Output Pin Period: the period of the PWM is defined by a Modulus Counter channel. A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly. B1 Value: define the trailing edge (or duty cycle) of the PWM channel B2 Value: buffered value of trailing edge B1 update: transfer from B2 to B1 takes place at A1 match EDPOL: define the output polarity A2 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 85 eDMA TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. enhanced Direct Memory Access (eDMA) ► DMA is often an alternative to CPU interrupt • • • ► Peripheral flag causes DMA request (instead of interrupt request) to transfer data Data is transferred from a “source” to a “destination” DMA channels have a “transfer control descriptor” (TCD) to describe this transfer Multiple different transfers can take place with a single DMA request using “channel linking” or “scatter gather” • Allows combining multiple peripherals to a new “super” peripheral Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 87 eDMA: Disabled Selecting a DMA source Source # 1 Source # 2 Source # 3 Peripherals . . . Source # 21 DMA Channel Mux Trigger # 1 Always Enabled DMA Channel #0 DMA Channel #1 . . . DMA Channel # 15 . . Trigger. # 4 • Software selects which DMA sources connect to the 16 DMA channels • DMA request for channels can be initiated by: • A peripheral (example: ADC conversion result ready to be put into queue) • Software (example: set a bit to initiate a block move) • Periodic Interval Timer (example: enable periodic transmit of latest pending SPI data) • Periodic Interval Timer available to 4 of the 16 channels (DMA channel 0 to 3) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 88 eDMA Mux: Channel Mux Source Options DMA Mux Source Input # # sources DMA Source 0 1 Channel Disabled 1 – 12 12 6x DSPIs : transmit, receive 13 – 24 12 6x eMIOS_A / 6x eMIOS_B channels 25 1 ADC_0 10-bit converion complete 26 1 ADC_1 12-bit conversion complete 27-28 2 IIC_A receive, transmit 29 - 32 4 Always Enabled - with PIT to generate periodic DMA - w/o PIT for continuous DMA transfer Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 89 eDMA Mux: Channel Configuration Channel Configuration Registers [0:15] TRIG (PIT generated DMA request) is only available for channels 0:7 (MPC5606B) • PIT timers 1:8 provide the TRIG for DMA channels 0:7 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 90 eDMA: ►Periodic • ► DMA channel triggering Triggering “throttles” DMA by limiting transfers Peripheral Request gates with Trigger to cause DMA Request “Always enabled” DMA sources: all Triggers generate DMA request Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 91 eDMA: ► Transfer Control Descriptor (TCD) Introduction One Transfer Control Descriptor (TCD) for each channel: • Source, Destination addresses • Separate Size for each read and write access • Number of transfers per DMA request • Total number of DMA requests serviced before stop or restart. • Signed restart address adjustment • Last Source Address Adjustment and Last Destination Address Adjustment • Scatter/Gather support Source Address (saddr) Signed Source Address Offset (soff) Transfer Attributes (smod, ssize, dmod, dsize) Inner “Minor” Byte Count (nbytes) Destination Address (daddr) Signed Destination Address Offset (doff) Current “Major” Iteration Count (citer) Last Source Address Adjustment (slast) Last Destination Address Adjustment (dlast_sga) “Major” Iteration Counter (biter) Channel Control Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM eDMA: Example Memory Array Current “Major” Loop Iteration Count (citer) 3 DMA Request . . . Minor Loop . . . Minor Loop . . . Minor Loop TCD Loops DMA Request Major Loop 2 DMA Request 1 ► Each DMA request initiates one minor loop transfer (iteration) without CPU intervention • DMA arbitration can occur after each minor loop. One level of minor loop DMA preemption is allowed ► The number of minor loops in a major loop = beginning iteration count (biter). Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 93 eDMA: addr: starting address size of one data transfer Minor Loop nbytes in minor loop (often the same value as size) . . . offset: number of bytes added to current address after each transfer (often the same value as size) ► Each DMA source and destination has their own: • . . . • • • ► Minor Loop Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TCD Terms addr size offset last Peripheral queues typically have size and offset equal to nbytes. last: number of bytes added to current address after major loop (typically used to loop back) TM 94 eDMA: Modulo Feature ► Provides the ability to easily implement a circular data queue • Size of queue is a power of 2 ► mod, a 5-bit bit field, specifies which lower address bits are allowed to increment from their original value after the address + offset calculation • all upper address bits remain the same as in the original value. • If mod = 0 disables modulo feature ► Example: source address = 0x12345670; offset is 4 bytes so mod=4, allowing for a 24 byte (16-byte) size queue Transfer # Address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 Upper address bits retain their original value. Circular buffer address wraps to original value Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM eDMA: ► Scatter-Gather Feature Allows a DMA channel to use multiple TCDs • Enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources • Example use: linked list of LIN messages Example: TCD B TCD A (in flash or SRAM) (in flash or SRAM) sga (Scatter Gather Address) sga Sequence: 1. Initialization: Load TCD A from flash to DMA channel x’s TCD 2. 1st DMA request or START=1: Executes TCD A; TCD B loads automatically 3. 2nd DMA request or START=1: Executes TCD B; TCD A loads automatically Option: TCD B could automatically execute with the 1st DMA request if the TCD’s start bit is set. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 96 eDMA: ► A DMA channel can “link” to another DMA channel, i.e, set the start bit of a 2nd TCD • • ► Channel Linking At the end of every minor loop (except the last one) And/or, at the end of the major loop Also enables linked lists Desired Link Behavior Link at end of Minor Loop Link at end of Major Loop TCD Control Field Name Description citer.e_link Enable channel-to-channel linking on minor loop completion (current iteration) citer.linkch Link channel number when linking at end of minor loop (current iteration) major.e_link Enable channel-to-channel linking on major loop completion major.linkch Link channel number when linking at end of major loop Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM eDMA: TCD Control Field Name start Other Control & Status Fields (1 of 2) Description Control bit to explicitly start channel when using a software initiated DMA service. (Automatically cleared by hardware after service begins.) (Note: Do not set START if DMA request comes from HW) active Status bit indicating the channel is currently in execution. done Status bit indicating major loop completion. (Set by hardware as CITER reaches 0. Cleared by software if using software initiated DMA service request.) d_req Control bit to disable DMA request at end of major loop completion. • Clears channel enable bit, DMAERQ, at major loop completion so no additional DMA requests are recognized until channel is enabled again (Important for FIFOs – later) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM eDMA: Other Control & Status Fields (2 of 2) TCD Control Description Field Name BWC[0:1] e_sg int_half int_major Control bits for “throttling” bandwidth control of a channel. Control bit to enable scatter-gather feature. Control bit to enable interrupt when major loop is half complete (DONE = 0) Control bit to enable interrupt when major loop completes (DONE = 1) BWC - Bandwidth Control Forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar. 00 No DMA_Engine stalls (for inner loop) 01 reserved 10 DMA_Engine stalls for 4 cycles after each R/W 11 DMA_Engine stalls for 8 cycles after each R/W Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 99 eDMA: Summary Source Address (saddr) • Transfer Control Descriptor - Signed Source Address Offset (soff) 32-bytes of local memory. • 32-bit Source and Destination addresses Inner “Minor” Byte Count (nbytes) Last Source Address Adjustment (slast) • Transfer attributes selects the size increment/decrement options. Destination Address (daddr) Current Iteration Count (citer) and optional channel link control (citer.e_link, citer.linkch) • Iteration (minor loop) counter – runs to zero every activation. To initiate a software DMA transfer, software must: • set the “start” bit in TCD • later clear the “done” bit in TCD 0 0 0 0 0 0 Signed Destination Address Offset (doff) Last Destination Address Adjustment (dlast_sga) “Major” Iteration Count (biter) and optional channel link control (biter.e_link, biter.linkch) Channel Control & Status (bwc, linkch, done, active, e_link, e_sg, dreq, int_half, int_maj, start) DMASSTRT – DMA Set Start Request 0 Transfer Attributes (smod, ssize, dmod, dsize) 0 DMACDONE – DMA Clear Done Status 0 0 SSTRTQ[6:0] 0 0 0 0 0 0 CDONE[6:0] A write value of 15, sets corresponding A write value of 15, clears corresponding A value greater than 63 written will Start bit in TCD_15 descriptor Done bit in TCD_15 descriptor Set or clear Start and Done Bits, respectively Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 100 eDMA: Fixed-Priority Arbitration • • Preemption: • Chan0 Chan1 • Normally transfers must complete before another channel can initiate a transfer Fixed priority allows one level of preemption Example: Fixed Chan. Arbitration Chan11 Chan12 Chan13 Chan14 Chan15 ► Pro: Fastest latency for higher priorities. Prevents lower priority tasks from using too much DMA bandwidth in case of a high priority deadline. Con: Potential to use up DMA bandwidth if a channel is always active in highest priority group. Chan2 Chan3 Chan4 Chan5 Chan6 Chan7 Chan8 Chan9 Chan10 ► Channel Arbitration 4 7 8 5 9 14 2 10 6 15 0 13 11 3 1 12 Note: 0 is lowest priority Channel Linking Note: When the DMA executes a channel link, it sets the START bit of the target (link) channel. Then, the arbitration pipeline is flushed. At this point, the target channel is in the arbitration pool with all other channels requesting service. Arbitration occurs and the highest priority channel requesting service is selected to execute. Thus higher priority channels will not be starved. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 101 Capture waveforms using eMIOS and DMA • Input Pulse-Width Measurement (IPWM) Mode – CBDR captures rising adges, CADR captures falling edges • DMA is triggered on falling edges at CADR capture) • DMA stores timing values (timebase is i.e internal counter) from CADR/CBDR into RAM • Interrupt generation at the end of major loop PWM C1 Falling PWM C1 Rising Source 16 bit register PWM C2 Falling saddr (source address) = eMIOS CADR register daddr (destination addr.) = start of memory queue nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop) ssize = 16 bits (read 1 halfword per transfer) soff = 4 bytes (src. addr. increment after transfer) slast = 0 (no src. addr. adjustment when done) smod = 3 (wrap address after each minor loop) dsize = 16 bits (write 1 half word per transfer) doff = 2 bytes (add 4 to dest. addr after each transfer) dlast = -32 bytes (restart daddr to start when done) dmod = 0 (disbaled) PWM C2 Rising eMIOS CADR register eMIOS CBDR register PWM C3 Falling . . . PWM C3 Rising PWM C4 Falling PWM C4 Rising PWM C5 Falling PWM C5 Rising PWM C6 Falling PWM C6 Rising INT_MAJ Enable an interrupt when major iteration count completes. PWM C7 Falling PWM C7 Rising PWM C8 Falling PWM C8 Rising Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 102 Generate waveforms using eMIOS and DMA • Waveform Period is defined by timebase – Unified Channel in MCB period • eMIOS is working in Double Action Output Compare Mode (DAOC) – CADR is programmed to trigger rising edge on timebase match, CBDR is programmed to trigger falling edge on timebase match • FLAG is set on second match and triggers DMA to write next waveform falling & rising edges to CADR/CBDR • Interrupt generation at the end of major loop PWM C1 Rising Destination 16 bit register PWM C1 Falling saddr (source address) = start of memory queue daddr (destination addr.) = eMIOS CADR register nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop) ssize = 16 bits (read 1 halfword per transfer) soff = 2 bytes (src. addr. increment after transfer) slast = -32 (restart saddr to start when done) smod = 0 (disbaled) dsize = 16 bits (write 1 half word per transfer) doff = 4 bytes (add 4 to dest. addr after each transfer) dlast = 0 bytes (disable) dmod = 3 (wrap address after each minor loop) PWM C2 Rising eMIOS CADR register PWM C2 Falling PWM C3 Rising PWM C3 Falling PWM C4 Rising PWM C4 Falling PWM C5 Rising . . . eMIOS CBDR register PWM C5 Falling PWM C6 Rising PWM C6 Falling PWM C7 Rising PWM C7 Falling PWM C8 Rising PWM C8 Falling INT_MAJ Enable an interrupt when major iteration count completes. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. TM 103 TM