By: Ali Mesgarani
Electrical and Computer Engineering
University of Idaho
1

Outline
 Motivation and goals
 Background
 New ADC topologies proposed for high speed, low power and medium resolution
 Asynchronous binary search ADC
 Pipeline binary search ADC
 Conclusion
2

Motivation





ADCs are key design blocks in modern microelectronic systems.
More signal-processing functions are implemented in the digital domain.
 Noise immunity
 Low power


Easy to design using CAD tools
Reproducibility, …
Today’s high speed communication systems have increased the demand for increased data rates, small area, and low power consumption.
High speed ADCs have significant importance in today’s digital signal processing and communication systems.
Designing energy efficient A/D converters by developing new architectures and circuits to take full advantage of what the modern process technologies have to offer.
3

Outline
 Motivation and goals
 Background
 New ADC topologies proposed for high speed, low power and medium resolution
 Asynchronous binary search ADC
 Pipeline binary search ADC
 Conclusion
4

Why do we need A/D converters?
 The real world is analog, but easier to process digital data.
 Speech, image, …
 Digital data needs to be carried on an analog signal
 Signal received at the antenna must be digitized.
 Analog signals contain too much unnecessary amount of data
 ADC samples the data and splits it into finite information
 ADC converts analog information to digital information
5

ADC at receiver in a link
DAC ADC
6

Analog to digital converter (ADC)
Analog
Sample
& Hold f sample
Digital
Quantization
7

Quantization
111
110
101
100
011
010
001
000
V
FSR
Δ V ,
V
LSB
V ref
8
4
V ref
8
7
8
V ref
Analog Input V in
111
110
101
100
011
010
001
000
1 2 3 4 5 6 7 8 Time
8

High speed ADC applications







Ultra Wide Band (UWB) communication
High Speed Serial Links
Digital Oscilloscope
Hard Disk Drive Read-Channel
Digital TV
Wireless Personal Area Network (WPAN)
Software Defined Radio
9

High speed ADC applications
Reference
Park, CICC’06
Chan, JSSC’08
Verbruggen
, JSSC’10
Harwood, ISSCC ‘07
Cao, JSSC ‘10
Uyttenhove , JSSC ‘03
Cao, ISSCC
‘08
Poulton , ISSCC ’02
Poulton
, ISSCC ‘03
Schvan,ISSCC
‘8
Van der Plas,ISSCC
‘06
Resolution (bits)
5.0
7.0
6.0
4.5
6.0
6.0
6.0
8.0
8.0
10.0
4.0
Speed (GS/s)
3.50
5.00
2.60
12.50
10.00
1.30
1.30
4.00
20.00
1.35
1.25
Power (mW)
227.0
-
2.2
-
10000.0
545.0
600.0
4600.0
10000.0
420.0
2.5
Application
UWB
UWB
UWB
Serial links
Serial links
Hard disk drive read-channel
Hard disk drive read-channel
Digital oscilloscope
Digital oscilloscope
Digital TV
WPAN
10

ADC topologies
 Flash
 Pipeline
 Successive Approximation Register (SAR)
 Sub-ranging
 Ramp
 Single slope
 Dual slope
 Delta-Sigma
11

Flash ADC
 N-bit flash: 2 N -1 comparators
 V in connected with 2 N comparators in parallel
-1
 Comparators connected to resistor string
R/2
V ref
V in
R
R
R
R
R
R
R
R/2
Over range
(2
N
-1) to N encoder
D
0
D
1
D
N-1
12

Flash ADC pros and cons
 Pros
 Very fast
 Cons
 Area and power increase exponentially with resolution
 Input capacitive loading on V in
 Noise
 Offset
 Jitter sensitivity
13

Pipelined A/D converters
 Widely used where high resolution and high throughput is required
 A pipeline A/D converter is a multi-step amplitude quantizer
 Cascade of stages of low-resolution analog-to-digital converters
 Trades latency for speed
14

Pipeline A/D converters
Coarse quantizer
15

Pipeline A/D converter Pros and Cons
 Pros
 High throughput
 Easy upgrade to higher resolutions
 Cons
 Latency
 High demands on speed and gain of amplifier(s)
 High power
16

SAR ADC
 Based on binary search
 Consisted of a comparator, N-bit DAC, binary search logic


Compare V
D/A
Modify V
D/A with input signal V in by D
0
D
1
D
2
…D
N-1 until closest possible value to V in is reached
 Sequential converter
V in
S&H
V
D/A
Logic
D
0
D
1
DAC
D
N-1
Successive Approximation
Register (SAR) ADC
V ref
17

3-bit SAR ADC example
7
V ref
8
V in
4
8
V ref
V ref
8
V
D/A
1.
2.
Iterations
3.
final result
1 00
1 1 0
11 1
10 1
01 1
0 1 0
00 1
011
010
001
000
111
110
101
100
18

SAR ADC pros and cons
 Pros
 Small area
 Low power
 Cons
 Low speed: N clock cycle for N-bit SAR ADC.
 Complex clock generation at high sampling rates:
 A 6 bit 300MS/s SAR ADC requires 2.1 GHz clock generator with low skew.
 Clock generator consumes more power than the ADC itself!
19

Resolution vs sampling rate of ADCs


SAR ADCs are the most energy efficient ADC topologies but low speed
Can we design ADCs with efficiency of SAR and speed of flash converters.
20

Asynchronous SAR ADC
 Problems with SAR
 The logic delay in the feedback takes up to 75% of clock cycle
 Complex clock generation
 Solution: Asynchronous SAR/Binary Search ADC
 No complex clock gen.
 No binary search logic
4.5/8
0
1
ABS ADC
1
0
0
1
21

Asynchronous SAR ADC
 Unroll feedback loop
 N comparators are used.
 Asynchronous clock is generated from MSB to
LSB.
 Speed is limited by N comparator delays and
DAC delays
22

Asynchronous SAR pros and cons
 Pros
 Can operate faster than conventional SAR
 No need for high speed clock generation
 Cons
 Offset between comparators
 High resolution cannot be achieved like SAR because of the offset.
 Larger area
23

Outline
 Motivation and goals
 Background
 New ADC topologies proposed for high speed, low power and medium resolution
 Asynchronous binary search ADC
 Pipeline binary search ADC
 Conclusion
24

Proposed ADC topologies
 Asynchronous topologies
 2-bit/stage Asynchronous Binary Search (ABS) ADC
 Hybrid topologies
 Pipeline Binary Search (PBS) ADC
25

Proposed ADC topologies
 Asynchronous topologies
 2-bit/stage Asynchronous Binary Search (ABS) ADC
 Hybrid topologies
 Pipeline Binary Search (PBS) ADC
26

2-bit/stage ABS ADC
 In a typical asynchronous SAR/binary search ADC speed is limited by N comparator, N DAC delays
 How to speed up?
 Resolve two bits in each stage (2-bit flash)
 Speed limited by N/2 comparator delays and DAC delays.
 Speed improvement by two times
 Penalty
 Power consumption increases by 1.5 times
27

2-bit/stage ABS ADC Operation
 Use a 2bit flash quantizer in each stage (3 comparators)
 Break the reference into 4 intervals.
 Combines sub-ranging and asynchronous processing ideas.
 Break the flash ADC operation into multiple steps
=9.5/16
0
=9.5/16
1
=9.5/16
1
=9.5/16
10/16
0
Asynch. CLK
=9.5/16
9/16
0
Asynch. CLK
=9.5/16
8/16
1
Asynch. CLK
28

2-bit/stage ABS ADC implementation
V in
φ
1a
From
MUX
φ
1b
C
1a
φ
1b
V ref,HI
φ
1a d
5
,d
4
V in
48
64
V in
32
64
SH
φ
1a
φ
1b
SH
φ
1a
φ
1b
V in
16
64
SH
φ
1a
φ
1b
-
+
+
-
φ
1bb
-
+
+
-
φ
1bb
-
+
+
-
φ
1bb
Resistive Ladder
Set
1
[0..3,0..2] d
3
,d
V in
SH
V a3 φ
1a en
V in
SH
V a2 φ
1a en
2
2
-
+
+
en
2b
V in
SH
V a1 φ
1a en
2 en
2
,en
2b
-
+
+
en
2b
-
+
+
en
2b a
1
,a
2
,a
3
,a
4
2
φ
1a
φ
1b en
2 en
3 data latch
XXXXX d
5 d
4
XXXX d
5 d
4 d
3 d
2
XX d
5 d
4 d
3 d
2 d
1 d latch
0
Set
2
V ref,LO
[0..15,0..2]
V in
SH
V b3 φ
1a en
3
V in
SH
V b2 φ
1a en
3
V in
SH
V b1 φ
1a en
3
-
+
+
en
3b
-
+
+
en
3b
-
+
+
en
3b en
3
,en
3b
XXXXXX XXXXd
1 d
0 d
1
,d
0
29

2-bit/stage ABS ADC simulation result
Parameters
Process
Feature size (nm)
Resolution (bits)
Supply (V)
Sampling rate (MS/s)
SNDR (dB)
Power (mW)
FoM (fJ/conv.step)
Value
RF CMOS, IBM
90
6
1.2
900
35.82
3.8
75
30

Proposed ADC topologies
 Asynchronous topologies
 2-bit/stage Asynchronous Binary Search (ABS) ADC
 Hybrid topologies
 Pipeline Binary Search (PBS) ADC
31

Pipelined Binary Search ADC
 How can we further speed up the binary search operation of Successive Approximation Register ADC?
 Can we operate the Successive approximation algorithm in pipeline fashion?
 By combining SAR and Pipeline architectures better performance than proposed ABS ADC were achieved.
 Two new topologies of PBS are developed.
32

Pipeline Binary Search (PBS) ADC




SAR-ADC loop has to be unrolled.
Sampled input signal has to be delayed by an analog delay line.
N-comparators and (n-1) digital to analog converters (DACs) have to be used
Speed is limited to 1 comparator delay and DAC delays
 How to delay an analog signal?
33

How to delay the analog signal?
 Digital delay can be easily implemented using a D-latch or
DFF
 Analog delay line is implemented by interleaved sampling of the analog signal
 Example: 2-clock cycle analog delay
34

6 bit, PBS ADC Circuit Implementation
 No opamp is used in this pipeline ADC
 Lower power, higher speed
35

Layout for the PBS1 ADC
DACs
R-String
Comparator
Sample&Holds
Clock ditribution
36

Simulation result for PBS1 ADC
Parameters
Process
Feature size(nm)
Resolution (bits)
Supply (V)
Sampling rate (GS/s)
SNDR (dB)
Power (mW)
FoM (fJ/conv.step)
Value
LLLVT CMOS, UMC
65
6
1.2
1.5
35.6
5.8
78
37

Comparison with state of the art ADCs
Technology (nm)
Resolution (bits)
# of channels
Sampling Rate (GS/s)
Peak SNDR (dB)
SNDR (dB)
Power (mW)
Supply (V)
FoM (fJ/cs)
ISSCC’8
130
6
2
1.20
35.0
28.0
32.0
1.0
980
JSSC’10 TCAS I’10 CICC ‘10 This work:PBS I ADC This work:ABS ADC
65
6
2
1.00
31.5
28.0
6.3
1.2
210
65
5
1
0.70
29.0
26.9
2.0
1.0
116
40
6
1
1.25
30.5
26.5
6.1
1.0
178
1.20
36.0
35.6
4.8
81
1.2
65
6
1
1.50
35.8
35.6
5.8
78
90
6
1
0.90
36.1
35.8
4.3
1.2
74
38

Summary





High speed and low power analog to digital converters are essential part of many communication and signal processing applications
In this research new ADC topologies that take the advantage of energy efficiency of SAR ADCs while enabling high speed operation compared with conventional SAR ADCs architectures is proposed.
A new 2 bit/stage ABS ADC was introduced
 Twice as fast as conventional ABS ADCs
A new ADC concept and implementation (PBS ADC) was introduced
 Enables binary search operation in a pipelined fashion
Application of asynchronous ADCs as quantizers for high resolution
ADCs
39

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