Dr A Sahu
Dept of Comp Sc & Engg.
IIT Guwahati
• 8085 & 8086 Architectures
• Peripheral Devices
– Display, Keyboard, Data Converter
• Combined Peripheral controller + timer (8155)
• Peripheral Controller
– Peripheral Controller (8255)
– Interrupt Controller (8259)
– DMA Controller (8237)
• Serial Communication controller (8251A)
• Programmable Interval Timer (8254)
Mid Semester Exam
• One page Data sheet of All Controller will be
provided
– Architecture, Control word, Status word, Mode
– 8155 iot, 8255ioc, 8259pic, 8237dma, 8251usart, 8254pit
• 5 questions (Order may be different)
– 2 Theory and Concepts
• (40 % Easy)
– 2 Design question
• (40 % can be done easily if u have attend the class)
– 1 Thinking question
• (20% ; relatively top level)
• Timing & Venue:
– 10.00AM-12.00Nn, 20 Sept 2010, 2202/2204
8085 Microprocessor Architecture
ReSeT6.5
INTR INTA RST5.5 RST7.5 TRAP
SID
Interrupt Control
SOD
Serial I/O Control
Bus 8 Bit
ACC
MUX
tmp R
IR
Flag
ALU
Timing and Control
I Decode
&
M/C
Encodin
g
W
Z
B
C
D
E
H
L
SP
PC
Inc/Dec. ter
Add latch
Add Buff
Data/Add Buff
Bus Interface
Unit
C BUS
Q6
Q5
Q4
Q3
Q2
Q1
SUM
CS (Code Seg Reg)
DS (Data Seg Reg )
ES (Extra Seg Reg )
SS (Stack Seg Reg)
IP (Intr Ptr)
Operand
InDirect
Execution
Unit
AH
BH
CH
DH
Sequencer
A BUS
SI (Source Idx )
DI (Dest. Idx)
BP (Base Ptr )
SP (Stack Ptr)
Z (Flag Reg)
AL
BL
CL
DL
Temp A
Temp B
Temp C
ALU
•
•
•
•
AX - the accumulator register (divided into AH / AL)
BX - the base address register (divided into BH / BL)
CX - the count register (divided into CH / CL)
DX - the data register (divided into DH / DL)
•
•
•
•
SI - source index register.
DI - destination index register.
BP - base pointer.
SP - stack pointer.
AH
AL
BH
BL
CH
CL
DH
DL
SI (Source Idx )
DI (Dest. Idx)
BP (Base Ptr )
SP (Stack Ptr)
Z (Flag Reg)
CS (Code Seg Reg)
DS (Data Seg Reg )
ES (Extra Seg Reg )
SS (Stack Seg Reg)
IP (Intr Ptr)
int A;
int B=10;
main(){
int Alocal;
int *p;
p=(int*)malloc(10);
}
Stack
Heap
BSS
Data
Code
.model small
.stack 100h ; reserve 256 bytes of stack space
.data
message db "Hello world, I'm learning Assembly$”
.code
main proc
mov ax, seg message ; ax<-data seg. start addr.
mov ds, ax ; Initialize Seg Reg
mov ah, 09 ; 9 in the AH reg indicates Procedure
;hould write a bit-string to the screen.
lea dx, message ;Load Eff Address
int 21h
mov ax,4c00h ; Halt for DOS routine (Exit Program)
int 21h
main endp
end main
• putchar( ‘a‘ ) ;
mov dl, ‘a‘
;dl = ‘a‘
mov ah, 2h ;character output subprogram
int 21h
; call ms-dos output character
• c = getchar() ;
mov ah, 1h
int 21h
mov c, al
; keyboard input subprogram
; char input, char is stored in al
; copy character from al to c
• Transmission Controller:
– MPU control, Device Control (DMA)
• Type of IO mapping
– Peripheral (IN/Out), Memory mapped IO (LD/ST,MV)
• Format of communication
– Synchronous (T & R sync with clock), Asynchronous
• Mode of Data Transfer
– Parallel, Serial (UART)
• Condition for data transfer
– Uncond., Polling, Interrupt, Ready signal, Handshake
D2
D1
D0
Digital
to
Analog
Converter
Vo
Analog
Output
Analog output
FS
7
6
5
4
3
2
1
0
LSB
000 001 010 011 100 101 110 111
Digital Inputs
• FullScaleOutput=(FullScaleValue – 1LSBValue)
• 1MSB Value=1/2 * FSV
Resolution, Reference Voltages, Settling Time,
Linearity, Speed, Errors
• Counter or Tracking ADC
• Successive Approximation ADC
– Most Commonly Used
• Parallel or Flash ADC
– Fast Conversion
7 Seg
9 Seg
16 Seg
3x5 DotMatix
5x7
9x11
Dot Matrix Display Panel
25x80 character monitor
40 Bit data line
2
0 1 3 4
Mod 5
Counter
Data 0
Data 1
Data 2
Data 3
Data 4
8 Bit data line
Row
Ctr
0
1
2
Col
Ctr
CLK > 50Hzx25x80
0 1 2 3 4 ….. 78 79
C A T
F I R E
23
24
25x80 character monitor
A
Decoder
Or
ROM
Memory
Decoded
Bits
Row
Ctr
0
Col
Ctr
CLK > 1024x768x50Hz
1 2 3 4 ….. …1023
0
1
2
1024x768 Pixel LCD
767
Frame Buffer
8x3=24 Bits
R B G
Refresh screen 50 time a Sec
+5V
0
1
2
14
3
. .
.
N to Lg(n) decoder
A B C D
0 0 1 1
15
C0
C1
C2
C6
C7
R0
Scan
Row
R6
R1
R2
Decode
to
ACSII
R6
6,3
R7
Scan Col: C2
(Memory
ROM)
To
Host
(CPU)
• Scan Row (6)
• Scan Column (3)
• Send this to Decoder to generate ASCII value or Scan code
CEb
CWR
AD0-AD7
Latc
h
Port
A
A0-A7
AL
E
D7-D0
A
2
A
1
A
0
3 to 8
Decoder
0
1
2
3
4
5
Port
B
Port
C
PA0-PA7
PB0-PB7
PC0-PC5
Timer
MSB
LSB
Clock for timer
Timer
Out
A
2
A
1
A Port
0
0
0
0 Comm/St
atus Reg
0
0
1 PA
0
1
0 PB
0
1
1 PC
1
0
0 Timer LSB
1
0
1 Timer
MSB
MSB
M2
M1
Timer
Command
D5
D4
IEB
IEA
D3
D2
PC
D1
D0
PB
PA
•
•
•
•
T1
0
T9
T8
T2
T1
T0
T6
•
M2, M1: mode bits:
–
–
T5
T4
T3
00: Single square wave of
wavelength TC/2 (TC/2,TC/2
if TC even; [TC+1/2],[TC-1/2]
if TC odd)
01: Square waves of
wavelength TC (TC/2,TC/2 if
TC even; [TC+1/2],[TC-1/2] if
TC odd)
10: Single pulse on the TC'th
clock pulse
11: Single pulse on every
TC'th clock pulse.
D0, D1: mode for PA and PB, 0=IN, 1=OUT
D2, D3: mode for PC
D4, D5: interrupt EN for PA and PB, 0=disable
1=enable
D6, D7: Timer command:
A
LT
D
3
D
2
PC5
PC4
PC3
PC2
PC1
PC0
1
0
0
IN
IN
IN
IN
IN
IN
2
0
1
OUT
OUT
OUT
OUT
OUT
OUT
–
–
–
3
1
0
OUT
OUT
OUT
STBA
BFA
INTRA
–
4
1
1
STBB
BFB
INTRB
STBA
BFA
INTRA
•
T11
T7
–
D6
T12
LSB
–
D7
T13
00: No effect
01: Stop if running else no effect
10: Stop after terminal count (TC) if running, else
no effect
11: Start if not running, reload at TC if running.
Port C bits (D2, D3)
Bi directional
Data Bus
D7-D0
Data
Bus
Buffer
RDb
WRb
A1
A0
RESET
8 bit Internal
Data Bus
Read
Write
Control
Logic
I/O
PA7-PA0
Gr A
Port A
(8)
Group A
Control
Group B
Control
Gr A
Port C
(H 4)
I/O
PC7-PC4
Gr B
Port C
(L 4)
I/O
PC3-PC0
I/O
PB7-PB0
Gr B
Port B
(8)
D7 D6
0/1
7
6
D7
D6
1 – mode select
0 – bit set/reset
5
D5
4
D4
3
D3
2
D2
1
0
D1
D0
BSR Mode
Bit Set/Reset
Group B
Port C(L) – 1 Input
0 output
Port B – 1 Input 0 output
Mode select: 0 mode 0; 1 mode 1
Port C(U) – 1 Input 0 output
Port A – 1 Input 0 output
Mode select: 00 mode 0;
01 mode 1; 1x mode 2
Group A
D4 D3 D2 D1 D0
I/O Mode
BSR Mode
Bit Set/Reset
Mode 0
Simple I/O
for Ports
A, B & C
For Port C
No Effect on
I/O Mode
CSb
D5
Mode 1
HS mode
for Ports
A and/or B
Port C bits
are used for
HS
Mode 2
Bidirectional
Data mode for
PortA
B can in mode 0/1
Port C bits are
used for HS
CSb
A1
A0
Sel
0
0
0
Port A
0
0
1
Port B
0
1
0
Port C
0
1
1
CRW
INTAb
Internal Bus
INT
Control Logic
IRQ0
RDb
WRb
CSb
A0
8 bit
Data Bus
IRQ1
IRQ2
IRQ3
IRQ4
8259A
Programmable
Interrupt
Controller
INT
INTAb
Interrup
t Service
Register
IRQ5
IRQ6
IRQ7
SPb/ENb
IRQ0
IRQ1
IRQ2
IRQ3
Interrupt
Request
Register
Priority
Resolver
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt Mask Register
CS
A0
Initialization
OCW
0
0
ICW1
OCW1
0
1
ICW2
ICW3,ICW4
OCW2,OCW3,
OCW4
Not Address
Not Address
1
X
AD
0
D7
1
T7
D6
T6
D5
T5
D4
T4
D3
T3
D2
T2
AD0
D
7
D D D
6 5 4
0
0
0
0
1
0 for x86
D1
T1
T7=T0 is the assign to IR0, Vector address for
ISR
D
2
D1
D0
LTIM
0
SGNL
IC4
0/1
Edge /Level
Trigger
1=single
0=Cascade
AD0
D7
D6
D5
D4
D3
D2
D1
D0
1
M7
M6
M5
M4
M3
M2
M1
M0
D0
T0
D3
Interrupt Masks: 1= Mask Set, 0 =Mask reset
AD0
D7
D6
D5
D4
D3
D2
D1
D0
0
R
SL
EOI
0
0
L2
L1
L0
Rote
ate
Spec
ific
EOI
IR Level to be
acted Upon (0-7)
To data Bus A7
A6
A5
To Address A4
Bus
DB0-DB7
DMA Req0
DMA Req 1
DMA Req 2
DMA Req 3
DREQ0
DREQ1
DREQ2
DREQ3
Hold Ack
A0-A3
A4-A7
HLDA
Clock
CLK
Reset
Ready
RESET
READY
Chip
Select
CSb
ADSTB
HOLD
Address Strobe
Hold request
DACK0
DACK1
DACK2
DACK3
DMA ack0
DMA ack1
DMA ack2
DMA ack3
IO/Mb
A4-A7
DB7-DB0
ADSTB
AEN
MEMRb
MEMWb
IORb
IOWb
End of Process
READY
RESET
CLK
HRQ
HLDA
EOPb
CMD
Req
Meaning
CH0 memory Add reg
CH0 Count reg
CH1 memory Add reg
CH1 Count reg
CH2 memory Add reg
CH2 Count reg
CH3 memory Add reg
CH3 Count reg
R/W status/Commnd reg
WR request reg
WR Single mask reg
WR mode reg
WR Clear byte ptr F/F
R/W Master Clear/Temp
WR Clear Mask Reg
WR all Mask clear bits
DREQ0
DREQ1
DREQ2
DREQ3
DACK0
DACK1
DACK2
DACK3
EOP
D6
D5
D4
D3
D2
D1
D0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
DACK Sense
Active
Low/High
DREQ
Sense Active
Low/High
Late/Extended
Write Selection
Fixed/
Rotating
Priority
Normal/
Compressed
Timing
Enable/Disable
Controller
Dis/En
CH0 Address
Hold
Dis/En
Mem-mem
Transfer
D6
00=Demand, 01=Single
10=Bloc, 11=Cascade
D
7
D
6
D
5
D
4
XXXXX
Don’t Care
Status
Reg Addr
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
D7
D7
Mode
b
A3
A2
A1
A0
IO Read
I/O Write
Memory Read
Memory Write
IORDb
IOWRb
MemRDb
MemWRb
CS
3 to 8
Decoder 00
D
3
D5
D4
D3
INC/DEC
Address
Dis/Ena
Auto Initialisation
00=verify Transfer
01=Write , 10=Read transfer
D2
D1
D0
Reset/Se
t REQ bit
00-11 Channel Select
00=CH0, 01=CH1,
10=CH2, 11= CH3
D
7
D
6
D
5
XXXX
Don’t Care
D
4
D2
D1
D0
Channel Select
00=CH0, 01=CH1, 10=CH2, 11=CH3
D3
D2
D1
D0
0/1
0/1
0/1
0/1
CH3 Mask Bit
CH2 Mask Bit
CH2 Mask Bit
CH0 Mask Bit
D7
D6
D5
D4
D3
D2
D1
D0
0/1, CH3
0/1,CH2
0/1, CH1
0/1, CH0
0/1, CH3
0/1, CH2
0/1, CH1
0/1, CH0
CH# Request
CH# Has reached TC
D7D0
RESET
CLK
C/Db
RDb
WRb
CSb
DSRb
DTRb
CTSb
RTSb
Data Bus
Buffer
R/W
Control
Logic
Modem
Control
Transmit
Buffer
I
n
t
e
r
n
a
l
Transmit
Control
Receive
Buffer
L
i
n
e
Receive
Control
TXD
TXRDY
TXE
TXC
RX
D
RXRDY
RXC
SYBDET
D7 D6 D5 D4 D3 D2 D1 D0
Framing Control
# of Stop bits
00:
01:
10:
11:
invalid
1 bit
1.5 bits
2 bits
CSb
C/Db
RDb
WRb
Meaning
1
X
X
X
Data Bus Tri-state
0
X
1
1
Data Bus Tri-state
0
1
0
1
Status  CPU
0
1
1
0
Control Word CPU
0
0
0
1
DataBuff  CPU
0
0
1
0
DataBuff  CPU
EH
IR
Parity Control
X0=No Parity
01: Even
11: Odd
00:
01:
10:
11:
5 bits
6 bits
7 bits
8 bits
00: Syn. Mode
01: x1 clock
10: x16 clock
11: x64 clock
ER
SBRK RxE
DTR
TxE
TxE:
transmit enable (0/1 Enable Disable)
DTR:
data terminal ready (1=ENABLE DTR)
RxE:
receiver enable (1/0=EN/DISABLE)
SBPRK: send break character 1= force TxD low
ER:
error reset (Reset Flags: Parity ,Over run,
Framing Error of Status Word)
RTS:
request to send (1= Enable Request to send)
IR:
internal reset (Reset 8251 to mode)
EH:
enter hunt mode (1=search for Sync
Character)
DSR
Character length Baud Rate
RTS
SYN
DET
TxRDY
RxRDY
TxEMPTY
PE
OE
FE
SYNDET
DSR
FE
OE
PE
Tx
RxRDY TxRDY
EMPTY
transmit ready (DB Buffer is empty)
receiver ready
transmitter empty
parity error (1=when PE detected)
overrun error
framing error (Aynsc only, Valid
stop bit not detected)
sync. character detected
data set ready (DSR set at 0 level)
D0-D7
Data
Bus
Buffer
RDb
WRb
A0
A1
I
n
t
e
r
n
a
l
Read/
Write
Logic
CSb
B
u
s
Control
Word
Register
Counter
0
CLK 0
GATE 0
OUT 0
Counter
1
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
Counter
2
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC2
RW1
RW0
M2
M1
M0
BCD
000
001
X10
X11
100
101
: Mode 0
:Mode 1
:Mode 2
:Mode 3
:Mode 4
: Mode 5
Select Counter
00: Counter 0
01: Counter 1
10: Counter 2
11: Read-Back
Command
Read Write
00: Counter latch
Command
01:RW LSByte only
10: RW MSByte
only
11:RW LSByte first
then Msbyte
•
•
•
•
•
•
0/1 =
Binary
/ BCD
Mode
Mode 0 : Interrupt on Terminal count
Mode 1 : Hardware Retriggerable One Shot
Mode 2 : Rate Generator
Mode 3 : Square wave generator
Mode 4 : Software Triggered Strobe
Mode 5 : Hardware Triggered Strobe
A1
A0
Selection
0
0
Counter 0
0
1
Counter 1
1
0
Counter 2
1
1
Control Register
D7
D
6
D5
D4
D3
D2
D1
D0
SC
1
SC
2
COUN
Tb
STATU
Sb
CNT
2
CNT
1
CNT
0
0
11:
ReadBack
Comma
nd
If (D5=0) count
is lateched
D3=1 select counter
2
D2=1 select counter
1
D1=1 select counter
0