Unit 3 Finite State Machine
If we hear, we forget;
if we see, we remember;
if we do, we understand.
-- Proverb
Department of Communication Engineering, NCTU
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3.1 Derivation of State Graphs and
Tables
Department of Communication Engineering, NCTU
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Hardware Project
Unit 3 Finite State Machine
Sau-Hsuan Wu

A Finite State Machine (FSM) is simply a state register
that holds the current state and some combinational logic
which calculates the next state and outputs based on the
current state and the inputs

FSM types


Moore machine : the outputs are functions of the present
state only
Mealy machine : the outputs are functions of both the
present state and the inputs
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
A Moore FSM

MTS turnstile
Initialization
Easy Cards
Passing
Locked
Unlocked
Passing
Violation
(Unlocked)
Alarm Reset
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
State diagram representation


Locked ST: S0, Unlocked ST : S1 and Violation ST: S2
Inputs




Presence of Easy Card  u0 =1, otherwise u0 =0
Passenger passing  u1 =1, otherwise u1 =0
Alarm reset  u2 =1, otherwise u2 =0
u0=0 XNOR u1=0
Outputs (Z)



S0  Locked
S1  Unlocked
S2  Unlocked
S0
u0=1
u1=1
u2=1
S2
u1=1
u2=0
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S1
u1=0
5
Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
State transition table
S+
S
Z
u2u1u0= 000 001 010 011 100 101 110 111
S0
S0
S1
S2
S0
S0
S0
S0
S0
1
S1
S1
−
S0
S1
−
−
−
−
0
S2
S2
−
S2
−
S0
S0
S0
S0
0
u0=0 XNOR u1=0
S0
u0=1
u1=1
u2=1
S2
u2=0
u1=1
S1
u1=0
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Binary state assignment
S+
S
Z
u2u1u0= 000 001 010 011 100 101 110 111
S0
S0
S1
S2
S0
S0
S0
S0
S0
1
S1
S1
−
S0
S1
−
−
−
−
0
S2
S2
−
S2
−
S0
S0
S0
S0
0
S
Q1+ Q0+
Q1 Q0
u2u1u0= 000 001 010 011 100 101 110 111
Z
00
00
01
10
00
00
00
00
00
1
01
01
−
00
01
−
−
−
−
0
10
10
−
10
−
00
00
00
00
0
11
−
−
−
−
−
−
−
−
−
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Unit 3 Finite State Machine
Hardware Project

Sau-Hsuan Wu
Next-State maps
Q1 Q0
Z
00
00
01
10
00
00
00
00
00
1
01
01
−
00
01
−
−
−
−
0
10
10
−
10
−
00
00
00
00
0
11
−
−
−
−
−
−
−
−
−
Q1Q0
00
u2
1/0
u2u1u0= 000 001 010 011 100 101 110 111
01
11
10
u1u0
01
0
11
0
0
X
0
0
X
0
X
0
X
0
X
Q1+
u2
1/0
0
1
10
0
1
X
1
X
11
11
0
0
01
X
0
X
01
X
0
X
u1u0
00
1
0
X
Q1Q0
X
X
0
1
0
X
X
0
X
X
10
0
0
X
1
X
X
0
0
0
X
X
0
X
X
10
0
X
X
0
X
X
0
X
0
Q0+
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Unit 3 Finite State Machine
Hardware Project

Characteristic equations
u1u0
Q1Q0
00
u2
1/0
01
11
10
u1u0
00
0
01
11
0
0
X
0
0
X
0
X
0
1
X
0
X
X
0
1
0
X
X
0
X
X
10
0
X
X
0
X
X
0
X
1
Q1+

Sau-Hsuan Wu
Q1+= Q1u2’ + Q0’u2’u1u0’
Q1Q0
00
01
00
01
0
0
0
X
X
10
0
0
1
X
1
u2
1/0 11
11
0
X
1
X
X
0
0
0
X
X
0
X
X
10
0
X
X
0
X
X
0
X
0
Q 0+
Q0+= Q0u1’ + Q0u0 + u2’u1’u0
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Hardware Project


Sau-Hsuan Wu
Output equations
Q1 Q0

Unit 3 Finite State Machine
u2u1u0= 000 001 010 011 100 101 110 111
Z
00
00
01
10
00
00
00
00
00
1
01
01
−
00
01
−
−
−
−
0
10
10
−
10
−
00
00
00
00
0
11
−
−
−
−
−
−
−
−
−/(1)
Characteristic equations:
Q1+= Q1u2’ + Q0’u2’u1u0’
Q0+= Q0u1’ + Q0u0 + u2’u1’u0
Output equation :
Z = Q1 Q0 (or = (Q1|| Q0)’
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Circuit realization with D-FFs


Characteristic equations:
Q1+= Q1u2’ + Q0’u2’u1u0’
Output equation :
Z = Q1  Q0
Q0+= Q0u1’ + Q0u0 + u2’u1’u0
Q1+
u2
D
Q
CK CLR
u1
u0
u1
Q1
Z
Q0+
D
u0
u2
Q
CK CLR
Q0
CLK
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Another Moore FSM

An elevator controller (Up, Down, Open and Timer start)
req > floor
u,d,o, t = 1,0,0,0
!(req > floor)
GoingUp
timer < 10
req > floor
!(timer < 10)
u,d,o,t = 0,0,1,0
Idle
req == floor
u,d,o,t = 0,1,0,0
DoorOpen
u,d,o,t = 0,0,1,1
req < floor
!(req<floor)
GoingDn
u is up, d is down, o is open
req < floor
t is timer_start
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The general model of a Moore machine
X1
X2
Q1+
D
Q
Q1
CK CLR
Q2+
Xm
Com.
Logic
D
Q
Q2
Com.
Logic
CK CLR
Qm+
D
Q
Qm
Z1
Z2
Zm
CK CLR
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
A Mealy FSM

A traffic light controller
Farmroad
C
HL
FL
Highw ay
Highw ay
HL
FL
C
Farmroad
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Hardware Project


Unit 3 Finite State Machine
Sau-Hsuan Wu
Tabulation of inputs and outputs
Input Signal
Reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
Tabulation of unique states
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The state diagram
Reset
S0: HG (FR)
TL’ + C’
S1: HY (FR)
S2: FG (HR)
TL & C /ST
S0
TS/ST
S3: FY (HR)
TS’
S1
S3
TS/ST
TS’
TL & C’/ST
S2
TL’ + C
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
TL’ + C’
Reset
State transition table
S0
TL & C /ST
HG = S0
FR = S0+ S1
HY = S1
FG = S2
HR = S2+ S3
FY = S3
ST = ?
TS’
TS/ST
TS’
S3
S1
TS/ST
TL & C’/ST
S2
TL’ + C
S+|ST
S
CTLTS =000
001
010
011
100
101
110
111
S0
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S1|ST
S1|ST
S1
S1|ST’
S2|ST
S1|ST’
S2|ST
S1|ST’
S2|ST
S1|ST’
S2|ST
S2
S2|ST’
S2|ST’
S3|ST
S3|ST
S2|ST’
S2|ST’
S2|ST’
S2|ST’
S3
S3|ST’
S0|ST
S3|ST’
S0|ST
S3|ST’
S0|ST
S3|ST’
S0|ST
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Hardware Project
Unit 3 Finite State Machine
Sau-Hsuan Wu
S+|ST
S
CTLTS =000
001
010
011
100
101
110
111
S0
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S0|ST’
S1|ST
S1|ST
S1
S1|ST’
S2|ST
S1|ST’
S2|ST
S1|ST’
S2|ST
S1|ST’
S2|ST
S2
S2|ST’
S2|ST’
S3|ST
S3|ST
S2|ST’
S2|ST’
S2|ST’
S2|ST’
S3
S3|ST’
S0|ST
S3|ST’
S0|ST
S3|ST’
S0|ST
S3|ST’
S0|ST
111
S+|ST
S
CTLTS =000
001
010
011
100
101
110
00
00 |0
00 |0
00 |0
00 |0
00 |0
00 |0
01 |1
01 |1
01
01|0
11 |1
01 |0
11 |1
01 |0
11 |1
01 |0
11 |1
11
11 |0
11 |0
10|1
10|1
11 |0
11 |0
11 |0
11|0
10
10 |0
00|1
10 |0
00|1
10 |0
00|1
10 |0
00|1
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Unit 3 Finite State Machine
Hardware Project
S+|ST
S
CTLTS =000
001
010
011
100
101
110
00
00 |0
00 |0
00 |0
00 |0
00 |0
00 |0
01 |1
01 |1
01
01|0
11 |1
01 |0
11 |1
01 |0
11 |1
01 |0
11 |1
11
11 |0
11 |0
10|1
10|1
11 |0
11 |0
11 |0
11|0
10
10 |0
00|1
10 |0
00|1
10 |0
00|1
10 |0
00|1
Q1Q0
00
C
1/0
Sau-Hsuan Wu
01
11
10
TLTS
0
01
11
0
0
0
0
0
1
0
1
1
1
0
0
Q1+
C
1/0
0
1
10
1
0
1
1
1
11
11
0
0
01
1
1
0
01
1
0
1
TLTS
00
0
1
1
Q1Q0
0
1
0
1
0
1
1
0
1
1
10
1
0
0
1
1
1
1
0
0
1
1
1
10
0
1
1
1
0
0
0
111
0
0
0
0
Q0+
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Unit 3 Finite State Machine
Hardware Project
S+|ST
S
CTLTS =000
001
010
011
100
101
110
00
00 |0
00 |0
00 |0
00 |0
00 |0
00 |0
01 |1
01 |1
01
01|0
11 |1
01 |0
11 |1
01 |0
11 |1
01 |0
11 |1
11
11 |0
11 |0
10|1
10|1
11 |0
11 |0
11 |0
11|0
10
10 |0
00|1
10 |0
00|1
10 |0
00|1
10 |0
00|1
Q 1Q 0
00
C
1/0
Sau-Hsuan Wu
01
11
10
TLTS
0
01
11
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
1
0
10
1
1
1
0
1
111
0
HG = S0
FR = S0+ S1
HY = S1
FG = S2
HR = S2+ S3
FY = S3
ST = Q1Q0’ TS + Q1’ Q0 TS +
Q1’ Q0’ CTL + Q1Q0C’TL
ST
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The general model of a Mealy machine
X1
X2
Z1
Z2
Xm
Zm
Q1+
D
Com.
Logic
Q
Q1
CK CLR
Q2+
D
Q
Q2
CK CLR
Qm+
D
Q
Qm
CK CLR
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Unit 3 Finite State Machine
Hardware Project

Circuit realization using a Mealy machine
Plant
ST
Sau-Hsuan Wu
D
Q
D
CK CLR
TL’ + C’
Reset
S0
TL & C /ST
Q
CK CLR
TS’
CLK
TS/ST TS’
S3
S1
CntPre
VDD
TS/ST
Counter for TS
DN
D
S2
TL’ + C
TS
CK Pre
TL & C’/ST
FSM
Counter for TL
DN
D
TL
CK Pre
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Unit 3 Finite State Machine
Hardware Project
Sau-Hsuan Wu
Timing diagram using a Mealy machine

CLK
Q1Q0
S0
S1
S2
S3
TL
TS
C
TL’ + C’
Reset
HG = S0
S0
TL & C /ST
TS/ST
ST
CntPre
ST = Q1Q0’ TS + Q1’ Q0 TS +
Q1’ Q0’ CTL + Q1Q0C’TL
TS ’
S3
S1
TS/ST
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S2
TL & C’/ST
TL’ + C
23
Unit 3 Finite State Machine
Hardware Project

Sau-Hsuan Wu
An alternative realization with a Moore machine
Plant
VDD
Counter for TS
ST
TL’ + C’
Reset
TL & C
DN
ENA D
TS
TS
TS’
CK Pre
CLK
Counter for TL
S1
ST
TS
DN
ENA D
S0
ST’
TL
S3
ST
ST
S2
ST’
TS’
TL & C’
TL’ + C
FSM
CK Pre
ST = Q1Q0’ + Q1’ Q0
Notice: need more states to generate the Pre signal if needed!!
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Unit 3 Finite State Machine
Hardware Project

Sau-Hsuan Wu
Timing diagram using a Moore machine
CLK
Q1Q0
S0
S1
S2
S3
TL
TS
C
ST
TL & C
TS’
ST = Q1Q0’ + Q1’ Q0
TL’ + C’
Reset
HG = S0
S1
ST
TS
Department of Communication Engineering, NCTU
S0
ST’
ST
S2
ST’
TS
TS’
S3
ST
TL & C’
TL’ + C
25
Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The general model of a digital circuit
X1
X2
Z1
Z2
XP
ZQ
IN1
CS1
Plant
IN2
FSM
INR
CS2
CSM
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Difference between a Moore machine and a Mealy
machine


The outputs of a Moore FSM are synchronized with the
CLK, however the outputs of a Mealy machine are not
The disadvantages of Moore FSMs




In general, more states are required to generate outputs
The action of the plant that the FSM controls is always one
CLK period lagging behind the control signals
The above two points are right the advantages of Mealy FSMs
The disadvantages of Mealy FSMs


Outputs of FSMs must be
sampled with FFs if
synchronization is required
Glitches and spikes
CntPre
ST
D
Q
CK CLR
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D
Q
CK CLR
27
Hardware Project


Unit 3 Finite State Machine
Sau-Hsuan Wu
Serial data code converter
Design a code converter that convert an NRZ-coded bit
stream to a Manchester-coded bit stream
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Unit 3 Finite State Machine
Hardware Project



Sau-Hsuan Wu
Realize the code converter with a Mealy machine
Use a clock Clock2 which is twice the data rate
The only two possible input sequences are 00 and 11
S
S
X= 0
+
Reset
Z
X=1 X= 0
X=1
S0
S1
S2
0
1
S1
S0
−
1
−
S2
−
S0
−
0
S0
0 /0
S1
1/1
0/1 1/0
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S2
29
Unit 3 Finite State Machine
Hardware Project

Sau-Hsuan Wu
The timing diagram using the Mealy machine
CLK2
NRZ
0
0
1
1
1
0
1
1
0
1
0
1
0
0
1
S0
S1
S0
S2
S0
S2
S0
S2
S0
S1
0
1
1
0
1
0
1
0
0
1
Manchester
(ideal)
Z
(actual)
S0
0 /0
S1
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1/1
0/1 1/0
S2
30
Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Redesign the data converter with a Moore machine
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The timing diagram using the Moore machine
Output is oneclock lagging
behind the
input sequence
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3.2 Data Path and FSM
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
The general model of a digital circuit
X1
X2
Z1
Z2
XP
ZQ
IN1
CS1
Plant
IN2
FSM
INR
CS2
CSM
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
A plant usually includes

A data path over which data are processed
 A data path may include





An arithmetic and logic unit (ALU)
Registers
Counters
Decoders
Peripherals which may include
 Input devices like key boards and mice
 Storages devices like memories and disks
 Output devices




Communications interface like USB, RS232, and Eithernet
Speaker
Printer
Displays like LCD and 7-segment displays
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Data path and FSM go hand in hand in digital design






A signal processing scheme is usually partitioned into a
sequence of processing stages
Data path decides the number of stages the data is processed
and the paths of data flow in between the stages
Data at the outputs of each stage are stores in registers
The complexity or in other words the levels of logics in
each stage decides the processing speed
On the other hand the number of stages decides the
processing delay
FSM controls data’s movement in data path
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Unit 3 Finite State Machine
Hardware Project

Sau-Hsuan Wu
Data path for bubble sorting of 4 words
DIP
SW
Reg 0
CS0
MUX
B
MUX
A
CS1
COMP
A
Reg 1
CS4
Reg 2
B
CS2
A>B
A=B
CS5
S0 S1
Reg 3
S2 S3
CS3
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Draw a flow chart
Idle
Load B
N
St
N
Load Data
Counter -Load
Cnt3=0
Y
Load A
Cnt1=0
B>A
Cnt 0 --
Load LW
Cnt0=0
Cnt 0 = 2
Load HW
N
Cnt1=Cnt0
Cnt 1 --
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Checking the Timing diagram
CLK
Idle
St
Load
Cnt 3 XX
Cnt 0
Cnt 1
11
10
01
XX
00
10
XX
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39
Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
Sequential machines are commonly partitioned into data path units
and control units
Datapath Unit
Datapath Logic
Control inputs
Clock
FSM
Control
signals
Datapath
Registers

The synthesis of a sequential machine usually includes:

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Constructing the datapath units
Designing FSMs to control the data flow
Realizing the control signals
Checking the timing of signals
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3.3 Algorithm State Machine
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Hardware Project
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Arithmetic units :
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Arithmetic and logic units (ALU)
Storage registers
Logic for moving data :
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
through the system
between the computation units and internal registers
to and from the external environments
Control units are commonly modeled by
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Sau-Hsuan Wu
Datapath units consist of:
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Unit 3 Finite State Machine
State transition graphs (STGs)
Algorithm state machine (ASM) charts for FSM
A combined control-dataflow sequential machine is
modeled by ASM and datapath (ASMD) charts
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Hardware Project
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Sau-Hsuan Wu
Algorithm State Machine (ASM) Charts
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Unit 3 Finite State Machine
State transition graphs only indicate the transitions that
result from inputs
Not only does ASM display the state transitions, it also
models the evolution of states under the application of input
datas
An ASM chart is formed with three fundamental elements
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
Both Mealy and Moore machines can be represented by
ASM
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The outputs of a Moore machine are listed inside a state box
Conditional outputs (Mealy outputs) are placed in
conditional output boxes
Start
En
C <= C+1
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
A sequential machine is partitioned into a controller and a
datapath, and the controller is described by an ASM
The ASM chart can be modified to link to the datapath
that is under control of the ASM
The modified ASM is referred to as the algorithm state
machine and datapath (ASMD) chart
ASMD is different from ASM in that :
each of the transition path of an ASM is annotated with
the associated concurrent register operations of datapath
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
An ASMD chart for a up-down counter
Up-down counter
with asynchronous reset
Up-down counter
with synchronous reset
Count <= 0
Reset
Count <= 0
Count <= Count - 1
Start
Count <= Count + 1
Clr
Count <= Count - 1
Start
Up
Up
Count <= Count + 1
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Hardware Project

Unit 3 Finite State Machine
Sau-Hsuan Wu
ASM v.s. ASMD charts for a counter with enable
ASM chart
representation
Start
ASMD chart
representation
Start
En
En
C <= C+1
Enable DP
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Count <= Count + 1
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
A electronic dice game
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
Flowchart for dice game
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
Convert flowchart to state machine chart
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
State machine chart
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
State graph
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
Next-state map
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Hardware Project
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Unit 3 Finite State Machine
Sau-Hsuan Wu
Realization
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