Introduction to Programmable Logic
Devices and FPGAs
Edward Freeman
STFC Technology Department
Detector & Electronics Division
Lecture Outline

Introduction


FPGA Field Programmable Gate Array


Why Programmable Logic Devices and FPGAs
Architecture
Design Flow


Hardware Description Languages
Design Tools
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Why Programmable Logic
Devices and FPGAs
Programmable Logic is a Key Underlying Technology for PP Experiments.

First-Level and High-Level Triggering

Data Transport (Networks)

Computers interacting with Hardware (Networks)

Silicon Trackers (Millions of Data Channels)
Commercial Devices. Developments driven by Industry.
Telecomms, Gaming, Aerospace, Automotive, Set-top boxes….
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS DAQ/Trigger Architectures
CMS
Fully custom PP ASICs
Programmable Logic
DIGITAL
CPUs Commodity PCs
“Telecoms Network” ~ 1 Tbps
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics

Special Dedicated Logic Functions (not possible in CPUs)


Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing
Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom Designed
Printed Circuit Boards PCBs.
Commercial
Programmable Logic
Devices, FPGAs
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lecture Outline

Introduction


FPGA Field Programmable Gate Array


Why Programmable Logic Devices and FPGAs
Architecture
Design Flow


Hardware Description Languages
Design Tools
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Logic Gates
MOORE’S LAW
Transistor Switches
< 40 nm ! $$$
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
edward.freeman@stfc.ac.uk
Truth Table
(Look Up Table LUT)
SUM of PRODUCTS
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
edward.freeman@stfc.ac.uk
Truth Table
(Look Up Table LUT)
SUM of PRODUCTS
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks



Logic Functions implemented in Look Up Table LUTs.
Flip-Flops. Registers. Clocked Storage elements.
Multiplexers (select 1 of N inputs)
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
edward.freeman@stfc.ac.uk
Logic Block
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Look Up Tables LUTs





LUT contains Memory Cells to implement small logic functions
Each cell holds ‘0’ or ‘1’ .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
Configured by re-programmable SRAM memory cells
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
3 – 6 Inputs
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
SRAM
SRAM
Multiplexer MUX
edward.freeman@stfc.ac.uk
Static Random Access Memory
SRAM cells
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks

Larger Logic Functions built up by connecting many Logic
Blocks together
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks


Larger Logic Functions built up by connecting many Logic
Blocks together
Determined by SRAM cells
SRAM
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SRAM cells
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
 Synchronous Logic driven by a CLOCK
 Registers, Flip Flops (Memory)

Intermediate
New Output every clock edge
Inputs
Clock Rate determines speed
CLOCK
EDGES
edward.freeman@stfc.ac.uk
Register
Comb Logic Must meet Timing
=> Predictable circuits
Shift Registers,
Pipelines,
Finite State Machines
…
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic



Registers on outputs. CLOCKED storage elements.
Synchronous FPGA Logic Design, Pipelined Logic.
FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
FPGA Fabric
Special Routing for Clocks
Clock from Outside world (eg LHC bunch frequency)
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays
FPGA

Field Programmable Gate Array




‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Standard CMOS Integrated Circuit fabrication process as for
SRAM memory chips (Moore’s Law)
“Hard blocks” for complex high speed functions
Huge Density of Logic Block ‘Islands’
1,000 … 100,000’s
in a ‘Sea’ of Interconnects
edward.freeman@stfc.ac.uk
FPGA Architecture
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays
FPGA
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Input Output I/O Getting data in and out
1
0
2
7
General-purpose I/O
Up to
> 1,000
I/O “pins”
(several 100 MHz)
banks
0 through
7
3
6
4
Special I/O SERIALISERS
~ 10 Gbps transfer rates
5
Transceiver block
Differential pairs
FPGA
edward.freeman@stfc.ac.uk
Optical TRx
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lecture Outline

Introduction


FPGA Field Programmable Gate Array


Why Programmable Logic Devices and FPGAs
Architecture
Design Flow


Hardware Description Languages
Design Tools
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs


Design Capture.
High level Description of Logic Design.


Graphical descriptions
Hardware Description Language (Textual)
Textual HDL
Graphical State Diagram
When clock rises
If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Top-level
block-level
schematic
Graphical Flowchart
edward.freeman@stfc.ac.uk
Block-level schematic
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages








Language describing hardware (Engineers call it FIRMWARE)
Doesn’t behave like “normal” programming language ‘C/C++’
Describe Logic as collection of Processes operating in Parallel
Language Constructs for Synchronous Logic
Compiler (Synthesis) Tools recognise certain code constructs
and generates appropriate logic
Not all constructs can be implemented in FPGA!
2 Popular languages are VHDL , VERILOG
Easy to start learning… Hard to master!
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL
ENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
COMPONENT Declaration
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs

High level Description of Logic Design

Hardware Description Language (Textual)

Compile (Synthesis) into NETLIST.
Boolean Logic Gates.

Target FPGA Device




Mapping
Routing
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
Bit File for FPGA
END CIRCUIT=TEST;
Mapping


Commercial CAE Tools
(Complex & Expensive)
Logic Simulation
Packing
Design Flow
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Configuring an FPGA




Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Lose configuration when board power is
turned off.
Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card
Configuration takes ~ secs
JTAG Port
Configuration data in
Configuration data out
= I/O pin/pad
Programming
Bit File
= SRAM cell
SRAM
JTAG Testing
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Not just logic

Hard blocks (built into the FPGA)








High speed serialises (1Gb, 10Gb, hyper-transport ect)
Complex multiplier units (DSP)
Embedded processors (PPC404, PPC440, ARM Cortex-A9)
PCI express (Gen 2)
Multi clock multi phase clock managers.
Built in ultra fast RAMs
Programmable IO. (LVDS, SSTL and 100’s of others)
Plus the millions of gates of programmable logic from the
FPGA fabric its self.
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Serialisers

A number of types and speeds.




We are currently supporting projects with multi 1Gb Ethernet
readout.
10Gb is working in the lab and 1st boards are in testing now
PCI express endpoint (Gen 1)
Camera link
Can use off the self
switches to make
backend system
edward.freeman@stfc.ac.uk
PCI express
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Embedded processors and multipliers

Processors





Fast image processing and control loop feedback in C code
software. (20KHz image rate)
Large ping pong (image) frame buffer
System monitoring, house keeping, reporting and logging
Can also have an army of small “soft” processor cores
Multipliers (DSP blocks)

Complex FFT for machine frequency control.
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Block RAMs and Clock managers

Block RAMs




Small high speed buffers
Look up tables and scratch pads.
FIFO’s to help adjust data rates between processing blocks.
Clock Managers



Generate different frequency's from a reference clock.
Generate phase shits of the clocks.
Distribute the clocks to the different areas of the FPGAs
(Not of much interest but nothing works without them)
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Other technology you can add to an FPGA

Memory interfaces



Maths functions





DRAM, DDR, QDR, SRAM, ZBTRAM ect.
Industry standard memory modules DDR2, DDR3,
Floating point units
Complex Multiplier
Integer Add, Sub, Multiply, Div
Digital signal processing functions FFT, FIR, reed-solomon
encoders
Or any other digital system that can be described with custom
logic.
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays
FPGA











Large Complex Functions
Re-Programmability, Flexibility.
Massively Parallel Architecture
Processing many channels simultaneously cf MicroProcessor
Fast Turnaround Designs 
Standard IC Manufacturing Processes. Moore’s Law 
Mass produced. Inexpensive. 
Many variants. Sizes. Features. 
PP Not Radiation Hard 
Power Hungry 
No Analogue 
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Trends




State of Art is 32nm on 300 mm wafers
Top of range >500,000 Logic Blocks
>1,000 pins (Fine Pitched BGA)
Logic Block cost ~ 1$ in 1990
Today < 0.1 cent
1.00E+09
1.00E+08
1.00E+07
Number of LCs

1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1985
1990
1995
2000
2005
2010
2015
2020
2025
Year
Problems


1
Power. Leakage currents.
Design Gap

CAE Tools
0.1
$ / LC

0.01
0.001
?
edward.freeman@stfc.ac.uk
0.0001
1990
1995
2000
2005
2010
2015
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary

FPGA Field Programmable Gate Arrays


Architecture
Design Flow



Hardware Description Languages
Design Tools
Exploit industry hardware and protocols
Importance for Particle Physics Experiments
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
References and contacts

The Design Warrior’s Guide to FPGAs


FPGA manufacturer web sites



www.xilinx.com
www.altera.com
FPGA Online




Clive Maxfield, Newnes Elsevier
www.pldesignline.com
www.fpgajournal.com
www.doulos.com
Technology


Rob Halsall – Rob.Halsall@stfc.ac.uk
John Coughlan – John.Coughlan@stfc.ac.uk
edward.freeman@stfc.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)