The Monolithic 3D-IC
A Disruptor to the Semiconductor Industry
MonolithIC 3D Inc. Patents Pending
1
Monolithic 3D Provides an Attractive Path to…
LOGIC
Monolithic 3D
Integration
with Ion-Cut
Technology
Can be
applied to
many
market
segments
MEMORY
OPTOELECTRONICS
•
3D-CMOS: Monolithic 3D Logic Technology
•
3D-FPGA: Monolithic 3D Programmable Logic
•
3D-GateArray: Monolithic 3D Gate Array
•
3D-Repair: Yield recovery for high-density chips
•
3D-DRAM: Monolithic 3D DRAM
•
3D-RRAM: Monolithic 3D RRAM
•
3D-Flash: Monolithic 3D Flash Memory
•
3D-Imagers: Monolithic 3D Image Sensor
•
3D-MicroDisplay: Monolithic 3D Display
MonolithIC 3D Inc. Patents Pending
FPGAs:
The 3D-TSV Solution
MonolithIC 3D Inc. Patents Pending
Reinventing FPGA using 3D-TSV
 Use different dies for:
 Programmable Logic
 Programmable I/O
 Programmable Memory
 Build Reticle Size with Multi-Dice Lines for each
 ~One Mask set with many die/functions size options
 Choice of process node and fabrication processes
MonolithIC 3D Inc. Patents Pending
Traditional FPGA Wafers vs. Continuous Array Wafers
FPGA
chip with
IO
Scribe
lanes
Scribe
lanes
IO “chiclet”
with TSV
prep
Traditional wafer of chips
TSVs
FPGA
Logic-only
chunk
TSV
Continuous Array of Logic at 22nm
Wafer of IO Chiclets at 0.15 m
MonolithIC 3D Inc. Patents Pending
Continuous Array Terrain Allows Defining Custom
Logic Sizes from Same Wafers
Chip
size 9
Chip
size 4
Scribe
lane
Chip
size 20
FPGA
Logic-only
chunk
 Long metal tracks cross scribe lines
 Die edges need to be sealed after cut
 Top wafer prepped for TSVs or micorbumps in standard pattern (“socket”) over logic
chunks
MonolithIC 3D Inc. Patents Pending
Assembling Continuous Array Terrain into
Customized Hybrid Stacks
Standard TSV
pattern
Chip
with
logic
size 9
Chip with TSV
visible
3D Hybrid
stack with
TSVs
TSV
prep
IO
0.15 m
memory
22 nm
SerDes
90 nm
• Chiclets
assembly actually happens prior to wafer
dicing
Chiclets
MonolithIC 3D Inc. Patents Pending
Advantages of 3D-TSV FPGA
 Good Fit for the End User Application with optimal size of
silicon - ~2-5 x cost reduction
 Wide range of technologies and function
 Reduce cost by using low cost old process for I/O
 Increase functionality to match user alternative SC
 Allow integration of additional vendors with their own dies
 Huge reduction of $$$ for masks
MonolithIC 3D Inc. Patents Pending
Future SoC New Logic  15%
MonolithIC 3D Inc. Patents Pending
FPGAs:
The Monolithic 3D Solution
MonolithIC 3D Inc. Patents Pending
3D IC Next Generation – Monolithic 3D
Monolithic 3D vs. TSV
(1:10,000 vertical connectivity ratio)
TSV: TSV-3D IC
Monolithic: Nu-3D IC
Layer Thickness
~50m
50-100nm
Via Diameter
~5m
~50nm
Via Pitch
~10m
~100nm
Limiting Factors
Wafer handling (~5m)
Aspect ratio (<10:1)
Lithography=>
Will keep scaling
Wafer (Die) to Wafer
Alignment
~1m
Layer to Layer Alignment
MonolithIC 3D Inc. Patents Pending
=> Will
keep scaling
Layer Transfer Technology (“Ion-Cut”)
 Defect-free single crystal formed @ <400oC
Oxide
Hydrogen implant
Flip top layer and
Cleave using 400oC
of top layer
bond to bottom layer
anneal or sideways
mechanical force. CMP.
p- Si
Top layer
Oxide
p- Si
Oxide
Bottom layer
p- Si
p- Si
H
Oxide
Oxide
Similar process (bulk-to-bulk) used for manufacturing all
SOI wafers today
MonolithIC 3D Inc. Patents Pending
12
Foundation – Pre-fabricated High Voltage
Programming Transistors (‘Older’ Process)
Cleavable wafer
‘Smart Cut’
Thin crystalline silicon layer
Oxide to oxide bonding
Programming
Transistors
Isolation
Transistors
High temp
interconnect
(tungsten)
MonolithIC 3D Inc. Patents Pending
Primary Device (‘House’) on top of the Foundation
Interconnect
Antifuses
House
Programmable
interconnect
Crystalline Silicon
MonolithIC 3D Inc. Patents Pending
Foundation
Crystalline Silicon (base wafer)
3D Antifuse Connectivity ~ ASIC Connectivity
M
N
M x N fully populated antifuse
crossbar
In the House
.
2
.
.
.
3
2
3
House
1
1
Foundation
VpVpVp+
VpVp+
VpVp+
M + N Programming Vp+
VpVp+
Vptransistors
Vp+
VpVp+
VpVp+
In the Foundation
VpVp+
Vp+
VpVp+
VpVp+ 3D Inc. Patents Pending
MonolithIC
VpVp+
Vp+
VpVp+
Future Monolithic 3D FPGA
 Multi-Tier Programmable Logic
 Tier 0 – The LUT Array + Local programmable interconnect
 Tier 1 – The Clock distribution Network + programmable power
distribution
 Tier 2 – Short Programmable Interconnect
 Tier 3 – Long Programmable Interconnect
 Reinvented PIC
 Antifuse
 1T Memory cell instead of the 6T
 Flash
 DRAM
…
MonolithIC 3D Inc. Patents Pending
Summary




Interconnects are now dominating all logic devices
Early innovations of 3D FPGA stimulate more ideas
FPGA vendors are moving into 3D (so far 2.5D)
Future FPGAs will utilize 3D technology to Reinvent the
FPGA
 TSV to re-architect the FPGA system
 Monolithic to re-architect the programmable logic fabric
 The Future is in the Third Dimension – 3D
MonolithIC 3D Inc. Patents Pending