ERD Logic Device Workshop
and ERD Business Meeting
Sept 22-23, 2008
Tsukuba, Japan
1 ERD WG 9/22-23/08
Work in Progress --- Not for Publication
Emerging Research Devices Working Group

Hiroyugi Akinaga
 Tetsuya Asai
 Yuji Awano
 George Bourianoff
 Michel Brillouet
 Joe Brewer
 John Carruthers
 Ralph Cavin
 U-In Chung
 Philippe Coronel
 Shamik Das
 Erik DeBenedictis
 Simon Deleonibus
 Kristin De Meyer
 Michael Frank
 Christian Gamrat
 Mike Garner
 Dan Hammerstrom
 Wilfried Haensch
 Tsuyoshi Hasegawa
 Shigenori Hayashi
 Dan Herr
 Toshiro Hiramoto
 Matsuo Hidaka
 Jim Hutchby
 Adrian Ionescu
 Kohei Itoh
 Kiyoshi Kawabata
 Seiichiro Kawamura
 Rick Kiehl
 Hiroshi Kotaki
2 ERD WG 9/22-23/08
AIST
Hokkaido U.
Fujitsu
Intel
CEA/LETI
U. Florida
PSU
SRC
Samsung
ST Me
Mitre
SNL
LETI
IMEC
AMD
CEA
Intel
PSU
IBM
NIMS
Matsushita
IBM
U. Tokyo
ISTEK
SRC
ETH
Keio U.
Renesas Tech
Selete
U. Minn
Sharp
Atsuhiro
Kinoshita
 Franz Kreupl
 Nety Krishna
 Zoran Krivokapic
 Phil Kuekes
 Lou Lome
 Hiroshi Mizuta
 Murali Muraldihar
 Fumiyuki Nihei
 Dmitri Nikonov
 Wei-Xin Ni
 Ferdinand Peper
 Yaw Obeng
 Dave Roberts
 Kaushal Singh
 Sadas Shankar
 Thomas Skotnicki
 Satoshi Sugahara
 Shin-ichi Takagi
 Ken Uchida
 Yasuo Wada
 Rainer Waser
 Franz Widdershoven
 Jeff Welser
 Philip Wong
 Kojiro Yagami
 David Yeh
 In-Seok Yeo
 In-K Yoo
 Peter Zeitzoff
 Yuegang Zhang
 Victor Zhirnov
Toshiba
Qimonda
AMAT
AMD
HP
IDA
U. Southampton
Freescale
NEC
Intel
NDL
NICT
NIST
Air Products
AMAT
Intel
ST Me
Tokyo Tech
U. Tokyo
Toshiba
Toyo U.
RWTH A
NXP
NRI/IBM
Stanford U.
Sony
SRC/TI
Samsung
SAIT
Freescale
LLLab
SRC
Work in Progress --- Not for Publication
Workshop and Business Meeting
Objectives (Sept. 22 – 23)

Layout roadmap for Carbon Nanotubes and Graphene for
“Ultimately Scaled CMOS” and “Beyond CMOS”. Build on
results from July ERD meetings.
–
–


Provide information needed to develop new Memory Table
entries for STT RAM (new TE for 2009).
Determine content for 2009 ERD logic section
–
–
–


Review Technology Entries (TEs) from 2007
Review potential TE adds/drops for 2009
Solicit writing volunteers for 2009
Discuss linkage to materials and architecture sections
–

Ultimate CMOS roadmap – potential solution (PIDS Role?)
Beyond CMOS roadmap entry – current ERD format?
How can we improve the integration? (e.g. joint workshops, key
materials properties table, …)
Approximate timeline for 2009
ERD Business meeting
3 ERD WG 9/22-23/08
Work in Progress --- Not for Publication
ITRS Emerging Research Devices
Workshops
Carbon-based Nanoelectronics
Organized by Dr. Yuji Awano - Fujitsu
Spin Transfer Torque RAM
Organized by Dr. U-In Chung - Samsung
Tsukuba International Congress Center
Tsukuba, Japan
September 22, 2008
9:30 – 15:00 and 15:10 – 19:00
4 ERD WG 9/22/08
Work in Progress --- Not for Publication
ERD Logic Devices and Business Meeting
Agenda (Sept. 23)
10:00
10:15
10:20
Welcome and Introductions
Prof. T. Hiramoto
Meeting Objectives and Agenda
G. Bourianoff
Layout roadmap for Carbon Nanotubes and
G. Bourianoff
Graphene for “Ultimately Scaled CMOS” and
“Beyond CMOS”. Build on results from July meetings.


11:30
Determine content for 2009 ERD logic section



12:00
12:45
13:30
G. Bourianoff
Review Technology Entries (TEs) from 2007
Review potential TE adds/drops for 2009
Solicit writing volunteers for 2009
Lunch
Continue determine content for 2009 ERD Logic Sect
Discuss linkage to materials and architecture sections


14:30
14:45
15:00
Ultimate CMOS roadmap – potential solution (PIDS Role?)
Beyond CMOS roadmap entry – current ERD format?
G. Bourianoff
M. Garner
How can we improve the integration? (e.g. joint workshops, M. Garner
key materials properties table, …)
Architecture section linkage to Logic Devices
Time line for 2009
Review Action Items
Adjourn
5 ERD WG 9/22-23/08
V. Zhirnov
J. Hutchby
J. Hutchby
Work in Progress --- Not for Publication
Scope of roadmap discussion




Integrate with other known technology roadmaps to
achieve commercial viability
Identify critical infrastructure requirements to
fabricate industrially relevant prototypes
Identify existing infrastructure & infrastructure gaps
Decide roadmap format – e.g. potential solution format
–
–
Decide major technology entries
Determine approximate timelines
6 ERD WG 9/22-23/08
Work in Progress --- Not for Publication
Carbon-based Nanoelectronics Workshop
Agenda
9:30 Introduction
9:40 “Theory of electronic states and
transport in graphene and nanotube”
10:30 “Graphene conduction control by gate
voltage
11:20 “Epitaxial graphene on Si substrate
mediated by an ultra-thin SiC layer”
12:10 Lunch
13:00 “Evaluation of number of graphene
layers grown on SiC”
13:50 “Beyond-CMOS applications of
graphene based nanoelectronics”
14:40 Summary
15:00 Spin Torque Transfer RAM Workshop
7 ERD WG 9/22/08
Dr. Y. Awano (Fujitsu)
Prof. T. Ando (Tokyo Inst. Tech)
Dr. K. Tsukagoshi (AIST)
Prof. M. Suemitsu (Tohoku U.)
Dr. H. Hibino (NTT)
Prof. P. Kim (Columbia U.)
Dr. Y. Awano (Fujitsu)
Dr. U-In Chung (Samsung)
Work in Progress --- Not for Publication
Carbon-based Nanoelectronics Workshop
Objectives


Determine status and current issues related to
broad area epitaxial growth of graphene
Determine application opportunities for carbonbased materials from both theoretical &
experimental points of view:



Ultimate scaling of CMOS
“Beyond CMOS” information processing
Determine how we should begin to roadmap
Carbon-based Nanoelectronics


Ultimately scaled CMOS
“Beyond CMOS” information processing
8 ERD WG 9/22/08
Work in Progress --- Not for Publication
Carbon-based Nanoelectronics Workshop
Questions
What are the gating challenges related to
epitaxial growth of graphene over large area?
 What are the key issues in applying graphene
to ultimately scaled MOSFETs?
 What new physical mechanisms does
graphene offer and how might we use them in
a new information processing paradigm?

9 ERD WG 9/22/08
Work in Progress --- Not for Publication
Spin Transfer Torque RAM Workshop
Agenda
15:10 Introduction
Dr. In-U Chung (Samsung)
15:20 (Manufacturing issues in High density STT MRAM) Dr. J. E. Lee (Samsung)
15:55 (Technology in High density perpendicular STT
Dr. H. Yoda (Toshiba)
MRAM)
16:30 (Scaling limit of STT MRAM)
17:05 Break
17:20 (Technology on Magnetic Tunnel Junction)
17:55 (Issues and solution for Dry Etching of STT MRAM)
18:30 Summary
19:00 Adjourn
(Topics but not presentation titles)
10 ERD WG 9/22/08
Work in Progress --- Not for Publication
Prof. H. Ohno (Tohoku U.)
Dr. E. Chen (Grandis)
Dr. V. Boccio (Veeco)
Dr. U-In Chung (Samsung)
Spin Transfer Torque RAM Workshop
Objectives
Identify Scaling limit of STT MRAM
 Identify Manufacturing issues
 Identify Current Status and Ultimate
Performance Metrics for the Memory Table

11 ERD WG 9/22/08
Work in Progress --- Not for Publication
Spin Transfer Torque RAM Workshop
Questions




What will be the most critical parameter for 22nm STT
MRAM?
: Retention (thermal stability ), Switching current (Jc),
Thermal stability, Etch slope, Endurance of Tunnel barrier
(MgO), TMR value (Variation)
What kind of MTJ can be solution for Post DRAM
Application ?
: Perpendicular MTJ or In-plane MTJ
What etch technology will be more suitable for 22nm STT
MRAM?
: RIE etch or Ion Beam etch?
What values of the parameters for the ITRS ERD Memory
Table are valid for STT RAM at 22nm?
12 ERD WG 9/22/08
Work in Progress --- Not for Publication
2008 ERD Update Schedule
















April 2 – Memory Workshop
April 2 – ERD Business Meeting
April 3 – 4 – ITRS Meetings (no public conference)
June ? – ERD Presentation draft for July 16 Conference due to Linda Wilson
July 10 – 11 Architecture Workshop & ERD Business Meeting
July 12 – ERD Business Meeting
July 14 – 15 – ITRS Meetings
July 16 – ITRS Public Conference
August 25 – ERD Chapter Update Material Due*
September 15 – 2008 ITRS Update Content Frozen*
September 22nd – Logic Workshop
September 23rd – ERD Business Meeting
December 6 – 2009 ERD Chapter Kickoff Meeting in Seoul, Korea
December 7 – 9 ITRS Meeting in Seoul, Korea
December 9 – ITRS Public Conference in Seoul, Korea
December 14 – 2009 ERD Chapter Kickoff Meeting in San Francisco @IEDM
* ERD typically uses the “update year” to prepare for the following “chapter
re-write year (i.e. 2009” and does not provide an update.
13 ERD WG 9/22/08
Work in Progress --- Not for Publication
2008 ERD/ERM Workshops
Workshop topic
Date
Location
Meeting
Emerging Research
Memory Devices
April
2008
Bonn,
Germany
ITRS
Spring
meeting
Emerging Research
Architectures
July 10-11
2008
San
Francisco,
CA, USA
Semicon
West
Maturity Eval for
selected ‘Beyond
CMO'S’
Technologies
July12-13,
2008
San
Francisco,
CA, USA
2
22
Done
Done
Evaluate 7 ERD Logic technologies for their
readiness for accelerated development
Done
Done
Emerging Research
Logic Devices
Sept.
2008
Tokyo,
Japan
Emerging Research
Materials
Nov. 10
2008
Austin,
USA
Emerging Research
Materials
March
2009
Tokyo, Japan
TX,
Specific technology entries
- Performance analysis for the various types of
memories
- Magnetic Race-Track Memory
- Nanowire Phase-Change Memory
- Polymer/Macromolecular Memory
- Chip Multiprocessors
- Memory Architectures
- Morphic Computational Architectures
-Turing-Heisenberg Rapprochement
SSDM
MMM*
- Nonlinear response functions
- Devices for “functional diversification”?
- Optimum circuit architectures associated with
novel devices
Materials for Spintronic Devices
- Energetics
- Transitions
- Time scales
- Interactions with external fields
Strongly Correlated Electron Materials
* 53rd Magnetism and Magnetic Materials Conference
14 ERD WG 9/22/08
Work in Progress --- Not for Publication
Action Items (1/2)
1.
Consider to include in the 2009 ERD Chapter the new chart entitled
“Evolution of Extended CMOS” contributed by ERD Japan.
Bourianoff
In Process
2.
Strengthen ties between US-EU-Asia. Requires good balance of
representing members from three regions
Hutchby
In Process
3.
The best demonstrated parameters are obtained from different
devices. Is it possible to obtain them simultaneously on one
device? We should include a note to this effect.
Bourianoff, Zhirnov
4.
Extend the Mission of ERD to include additional Research Vectors
proposed by the Japan ERD WG. These are Numbers 1 – 4
listed in Item No. 1 above.
Bourianoff
5.
Consider moving to PIDS in 2009: 1) III-V Alternate Channel
Materials, and 2) Low Dimensional Materials. Discuss this
with PIDS. (This discussion has begun.)
Bourianoff
6.
Make the mission of ERD clear. Make it more Globally justified.
Hutchby
7.
Organize an ERD Working Group in Korea
In U. Chung
15 ERD WG 9/22/08
Work in Progress --- Not for Publication
In Process
In Process
Action Items (2/2)
8.
Bob Doering argued that the Critical Evaluation Chart gives the
wrong message;
a.We need to re-think this chart
b.This chart assigns a different meaning to red than is used by
all the other ITRS chapters. The other chapters use red to
highlight a major research gap.
c.We should point the directions into which “critical path”
research should be directed.
We need a way to distinguish a Fundamental Limit versus the
Maturity of the Technology Entry
Hutchby
9.
Need a dialog with the Design and Systems Drivers ITWG to
address synergy between the two chapters.
Hutchby,
Bourianoff, Yeh
10.
Discuss/decide upon expanding scope to include Sensors, Actuators,
and Power Sources to encompass More than Moore or Functional
Diversification
Hutchby and
Brillouet
11.
Discuss other materials (in addition to NiO) for Fuse/Anti-fuse
Memory Tech
Zhirnov & Garner
12.
Plan Memory FXF Meeting in Germany for April 2, 2008. Include
Memory Expert Panel.
Zhirnov
Done
13.
Write paper/proposal for NSF Funding for workshops.
Hutchby/Zhirnov
Done
14.
Include Akinaga-san in Memory Working Group
Zhirnov
Done
16 ERD WG 9/22/08
Work in Progress --- Not for Publication
In Process